chan_err_map Entity Reference

Inheritance diagram for chan_err_map:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Generics
jfex	integer := 1

Ports
clock	in	std_logic
reset_0	in	std_logic
reset_1	in	std_logic
reset_2	in	std_logic
reset_3	in	std_logic
reset_4	in	std_logic
error_0	in	std_logic
error_1	in	std_logic
error_2	in	std_logic
error_3	in	std_logic
error_4	in	std_logic
sample_0	in	std_logic
sample_1	in	std_logic
sample_2	in	std_logic
sample_3	in	std_logic
sample_4	in	std_logic
chan_in	in	STD_LOGIC_VECTOR ( 4 downto 0 )
error_map_0	out	STD_LOGIC_VECTOR ( 23 downto 0 )
error_map_1	out	STD_LOGIC_VECTOR ( 23 downto 0 )
error_map_2	out	STD_LOGIC_VECTOR ( 23 downto 0 )
error_map_3	out	STD_LOGIC_VECTOR ( 23 downto 0 )
error_map_4	out	STD_LOGIC_VECTOR ( 23 downto 0 )

Detailed Description

Definition at line 34 of file chan_err_map.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/chan_err_map.vhd