RTL Architecture Reference

Processes
PROCESS_65	( clock )
PROCESS_66	( clock )
PROCESS_67	( clock )
PROCESS_68	( clock )
PROCESS_69	( clock )
PROCESS_70	( clock )
PROCESS_71	( clock )

Components
error_ila

Constants
last_chan	integer := 23

Signals
bit_sel	std_logic_vector ( last_chan downto 0 )
map_reg_0	std_logic_vector ( 23 downto 0 )
map_reg_1	std_logic_vector ( 23 downto 0 )
map_reg_2	std_logic_vector ( 23 downto 0 )
map_reg_3	std_logic_vector ( 23 downto 0 )
map_reg_4	std_logic_vector ( 23 downto 0 )
error_s_0	std_logic
error_s_1	std_logic
error_s_2	std_logic
error_s_3	std_logic
error_s_4	std_logic
reset_0_s	std_logic
reset_1_s	std_logic
reset_2_s	std_logic
reset_3_s	std_logic
reset_4_s	std_logic
chan_in_s	std_logic_vector ( 4 downto 0 )

Detailed Description

Definition at line 65 of file chan_err_map.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/chan_err_map.vhd