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ROD firmware
1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board
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--------------------------------------------------- Backplane Control Bus bit Definitions --------------------------------------------------- backplane_control(0): Full system Reset backplane_control(1): Reset all Aurora channels (and pipes, fifos) backplane_control(2): threshold counter reset backplane_control(3): backplane_control(4): readout contro link reset backplane_control(5): packet processor reset backplane_control(6): Full Mode soft reset backplane_control(7): clock_test_reset backplane_control(31): Reset input pipes and fifos (not aurora) More...
Entities | |
| RTL | architecture |
Libraries | |
| IEEE | |
Use Clauses | |
| STD_LOGIC_1164 | |
| std_logic_unsigned | |
| NUMERIC_STD | |
| ipbus | |
Generics | |
| channel_num | STD_LOGIC_VECTOR ( 11 downto 0 ) := " 000000000000 " |
| lmem | STD_LOGIC_VECTOR ( 3 downto 0 ) := " 0000 " |
| max_packet_length | STD_LOGIC_VECTOR ( 15 downto 0 ) := x " 02FF " |
| sim | integer := 0 |
| debug | integer := 1 |
| axi_fifo | integer := 0 |
| jfex | integer := 0 |
| bp_width | integer := 64 |
| fifo_instr | integer := 0 |
| length_lsb | integer := 20 |
| length_msb | integer := 31 |
Ports | ||
| ipb_clk | in | std_logic |
| ipb_rst | in | std_logic |
| ipb_in | in | ipb_wbus |
| ipb_out | out | ipb_rbus |
| aurora_chan_stat | in | STD_LOGIC_VECTOR ( 31 downto 0 ) |
| tob_fifo_busy_threshold | in | STD_LOGIC_VECTOR ( 15 downto 0 ) |
| bulk_fifo_busy_threshold | in | STD_LOGIC_VECTOR ( 15 downto 0 ) |
| tob_fifo_xoff_threshold | in | STD_LOGIC_VECTOR ( 15 downto 0 ) |
| bulk_fifo_xoff_threshold | in | STD_LOGIC_VECTOR ( 15 downto 0 ) |
| time_count | in | STD_LOGIC_VECTOR ( 31 downto 0 ) |
| aurora_channel_control | out | STD_LOGIC_VECTOR ( 31 downto 0 ) |
| backplane_control | in | STD_LOGIC_VECTOR ( 31 downto 0 ) |
| chan_disable | in | std_logic |
| init_clk | in | std_logic |
| bp_reg_reset | in | std_logic |
| master_reset | in | std_logic |
| wdog_fifo_reset | in | STD_LOGIC |
| RESET | in | std_logic |
| clk_160 | in | std_logic |
| rt_clk | in | std_logic |
| aurora_user_clk | in | std_logic |
| pp_clock | in | std_logic |
| s_axis_tvalid | in | std_logic |
| s_axis_tlast | in | std_logic |
| tob_s_tready | out | std_logic |
| s_axis_tdata | in | std_logic_vector ( ( bp_width- 1 ) downto 0 ) |
| poll_chan | in | std_logic |
| tob_m_tvalid | out | std_logic |
| tob_m_tlast | out | std_logic |
| tob_m_tready | in | std_logic |
| tob_m_tdata | out | std_logic_vector ( ( bp_width- 1 ) downto 0 ) |
| tob_header_marker | out | std_logic |
| tob_tail_marker | out | std_logic |
| hdr_crc_tag | out | std_logic |
| comb_error_tag | out | std_logic |
| calo_poll_chan | in | std_logic |
| calo_m_tvalid | out | std_logic |
| calo_m_fifo_tlast | out | std_logic |
| calo_m_axis_tready | in | std_logic |
| calo_s_axis_tready | out | std_logic |
| calo_m_axis_tdata | out | std_logic_vector ( ( bp_width- 1 ) downto 0 ) |
| calo_header_marker | out | std_logic |
| calo_tail_marker | out | std_logic |
| s_axi_ufc_rx_tdata | in | std_logic_vector ( 63 downto 0 ) |
| s_axi_ufc_rx_tvalid | in | std_logic |
| s_axi_ufc_rx_tlast | in | std_logic |
| channel_busy | out | std_logic |
| timeout_err | in | std_logic |
| L1A | in | std_logic |
--------------------------------------------------- Backplane Control Bus bit Definitions --------------------------------------------------- backplane_control(0): Full system Reset backplane_control(1): Reset all Aurora channels (and pipes, fifos) backplane_control(2): threshold counter reset backplane_control(3): backplane_control(4): readout contro link reset backplane_control(5): packet processor reset backplane_control(6): Full Mode soft reset backplane_control(7): clock_test_reset backplane_control(31): Reset input pipes and fifos (not aurora)
aurora_channel_control(0): Channel Reset aurora_channel_control(1): clear channel error counters aurora_channel_control(2): Channel Disable aurora_channel_control(3): TOB fifo reset aurora_channel_control(4): Bulk fifo reset aurora_channel_control(6): TOB FIFO XOFF aurora_channel_control(7): Bulk FIFO XOFF aurora_channel_control(29): FEX reset out (feeds Readout_Control) aurora_channel_control(30): Aurora channel reset (timed) (also resets input fifos) aurora_channel_control(31): Aurora channel GT reset (timed)
Definition at line 94 of file channel_fifo.vhd.
1.9.1