RTL Architecture Reference

Processes
PROCESS_72	( aurora_user_clk )
PROCESS_73	( aurora_user_clk )
PROCESS_74	( aurora_user_clk )
PROCESS_75	( pp_clock )
PROCESS_76	( pp_clock )
PROCESS_77	( aurora_user_clk )
PROCESS_78	( pp_clock )
PROCESS_79	( pp_clock )
PROCESS_80	( pp_clock )
PROCESS_81	( pp_clock )
PROCESS_82	( pp_clock )

Components
aurora_pipe	<Entity aurora_pipe>
clock_cross_fifo
dual_input_fifo_4K
jfex_test_fifo_2	<Entity jfex_test_fifo_2>
axis_input_fifo
aurora_fifo_in_ila
aurora_fifo_out_ila
data_fifo_vio
fex_chan_regs	<Entity fex_chan_regs>
ufc_rx	<Entity ufc_rx>
pulse_stretch	<Entity pulse_stretch>

Signals
m_axis_tready	STD_LOGIC
tob_m_axis_tdata	STD_LOGIC_VECTOR ( ( bp_width- 1 ) downto 0 )
axis_data_count	STD_LOGIC_VECTOR ( 31 downto 0 )
axis_wr_data_count	STD_LOGIC_VECTOR ( 10 downto 0 )
axis_rd_data_count	STD_LOGIC_VECTOR ( 10 downto 0 )
s_axis_aresetn	STD_LOGIC
m_axis_aresetn	STD_LOGIC
tvalid_prev	STD_LOGIC := ' 0 '
first_cyc	STD_LOGIC
poll_reg	STD_LOGIC := ' 0 '
len_count	STD_LOGIC_VECTOR ( 11 downto 0 )
frag_length	STD_LOGIC_VECTOR ( 11 downto 0 )
t_last_delay	STD_LOGIC
no_complete_frag	STD_LOGIC
m_fifo_tlast	STD_LOGIC
rd_len_fifo	STD_LOGIC
hdr_length	STD_LOGIC_VECTOR ( ( length_msb- length_lsb ) downto 0 )
length_error	STD_LOGIC
pipe_m_tval_tob	STD_LOGIC
tob_fifo_en	STD_LOGIC
pipe_m_tval_calo	STD_LOGIC
calo_fifo_en	STD_LOGIC
calo_fifo_tvalid	STD_LOGIC
tob_fifo_tvalid	STD_LOGIC
tob_axis_rd_data_count	STD_LOGIC_VECTOR ( 31 downto 0 )
tob_axis_wr_data_count	STD_LOGIC_VECTOR ( 31 downto 0 )
calo_axis_data_count	STD_LOGIC_VECTOR ( 31 downto 0 )
calo_axis_wr_data_count	STD_LOGIC_VECTOR ( 31 downto 0 )
calo_axis_rd_data_count	STD_LOGIC_VECTOR ( 31 downto 0 )
calo_int_axis_tready	STD_LOGIC
calo_poll_reg	STD_LOGIC := ' 0 '
calo_header_marker_i	std_logic
calo_tail_marker_i	std_logic
cc_int_axis_tready_i	STD_LOGIC
cc_poll_reg	STD_LOGIC := ' 0 '
tob_header_marker_i	std_logic
tob_tail_marker_i	std_logic
cc_tob_fifo_en	std_logic
s_axis_tready_i	std_logic
m_tvalid_i	std_logic
tob_trans	std_logic
tob_buf_tvalid	std_logic
calo_s_axis_tready_i	std_logic
calo_m_tvalid_i	std_logic
calo_m_fifo_tlast_i	std_logic
calo_m_axis_tdata_i	std_logic_vector ( 63 downto 0 )
fifo_vio_reset	std_logic
reset_i	std_logic
RESET_stretch_i	std_logic
tob_fifo_reset	std_logic
bulk_fifo_reset	std_logic
n_tob_fifo_reset	std_logic
n_bulk_fifo_reset	std_logic
aurora_channel_control_i	STD_LOGIC_VECTOR ( 31 downto 0 )
pipe_m_axis_tvalid	std_logic
pipe_m_axis_tlast	std_logic
pipe_m_axis_tdata	std_logic_vector ( 63 downto 0 )
pipe_m_first_cyc	std_logic
s_crc_error	std_logic
m_crc_error	std_logic
tob_m_axis_tuser	std_logic_vector ( 3 downto 0 )
calo_m_axis_tuser	std_logic_vector ( 3 downto 0 )
crc_tag	std_logic
hdr_crc_tag_i	std_logic
pkt_len_violation	STD_LOGIC
ufc_message	STD_LOGIC_Vector ( 7 downto 0 )
ufc_parity_error	STD_LOGIC
ufc_channel_busy	STD_LOGIC
ufc_parity_disable	std_logic
test_signal	STD_LOGIC
comb_error	STD_logic
pipe_m_comb_error	STD_LOGIC
last_l1id	STD_LOGIC_vector ( 31 downto 0 )
current_l1id	STD_LOGIC_vector ( 31 downto 0 )
first_event	STD_LOGIC
repeat_l1id_counter	STD_LOGIC_vector ( 31 downto 0 )
repeat_l1id_counter_reset	STD_LOGIC
packets_read_counter	STD_LOGIC_vector ( 31 downto 0 )
packets_read_counter_reset	STD_LOGIC

Instantiations
pulse_stretcher	pulse_stretch <Entity pulse_stretch>
input_pipe	aurora_pipe <Entity aurora_pipe>
clk_cross_tob_fifo	dual_input_fifo_4k <Entity dual_input_fifo_4k>
clk_cross_tob_fifo	jfex_test_fifo_2 <Entity jfex_test_fifo_2>
calo_fifo	dual_input_fifo_4k <Entity dual_input_fifo_4k>
clk_cross_tob_fifo	axis_input_fifo
calo_fifo	axis_input_fifo
tob_fifo_in_ila	aurora_fifo_in_ila
tob_fifo_out_ila	aurora_fifo_out_ila
calo_fifo_out_ila	aurora_fifo_out_ila
channel_fifo_vio	data_fifo_vio
ufc_receiver	ufc_rx <Entity ufc_rx>
status_regs	fex_chan_regs <Entity fex_chan_regs>

Detailed Description

Definition at line 202 of file channel_fifo.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/channel_fifo.vhd