jfex_test_fifo_2 Entity Reference

Inheritance diagram for jfex_test_fifo_2:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Ports
m_aclk	in	STD_LOGIC
s_aclk	in	STD_LOGIC
s_aresetn	in	STD_LOGIC
s_axis_tvalid	in	STD_LOGIC
s_axis_tready	out	STD_LOGIC
s_axis_tdata	in	STD_LOGIC_VECTOR ( 63 DOWNTO 0 )
s_axis_tlast	in	STD_LOGIC
s_axis_tuser	in	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
m_axis_tvalid	out	STD_LOGIC
m_axis_tready	in	STD_LOGIC
m_axis_tdata	out	STD_LOGIC_VECTOR ( 63 DOWNTO 0 )
m_axis_tlast	out	STD_LOGIC
m_axis_tuser	out	STD_LOGIC_VECTOR ( 3 DOWNTO 0 )
axis_wr_data_count	out	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
axis_rd_data_count	out	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
timeout_err	in	std_logic

Detailed Description

Definition at line 35 of file jfex_test_fifo_2.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/jfex_test_fifo_2.vhd