RTL Architecture Reference

Processes
PROCESS_203	( m_aclk )

Components
aurora_in_fifo
processor_in_fifo
ila_input_fifo
ila_clk_cross_fifo

Signals
mid_fifo_tvalid	std_logic
mid_fifo_tready	std_logic
mid_fifo_tdata	std_logic_vector ( 63 downto 0 )
mid_fifo_tlast	std_logic
mid_fifo_tuser	std_logic_vector ( 3 downto 0 )
axis_data_count_i	std_logic_vector ( 31 downto 0 )
axis_data_count	std_logic_vector ( 31 downto 0 )
s_areset	std_logic
timer	std_logic_vector ( 31 downto 0 )
mid_fifo_wr_data_count	std_logic_vector ( 9 downto 0 )
mid_fifo_rd_data_count	std_logic_vector ( 9 downto 0 )
s_axis_tready_i	std_logic
start_timer	STD_LOGIC
stop_timer	STD_LOGIC
run_timer	STD_LOGIC
packet_count	STD_LOGIC_VECTOR ( 7 downto 0 )
m_axis_tvalid_i	STD_LOGIC
m_axis_tlast_i	STD_LOGIC
m_axis_tdata_i	STD_LOGIC_VECTOR ( 63 downto 0 )
m_axis_tuser_i	STD_LOGIC_VECTOR ( 3 downto 0 )
timeout_err_reg	STD_LOGIC
s_axis_tvalid_safe	STD_LOGIC
mid_fifo_tvalid_safe	STD_LOGIC
m_axis_tready_safe	STD_LOGIC
clk_cross_wr_rst_busy	STD_LOGIC
input_wr_rst_busy	STD_LOGIC

Instantiations
clk_cross_fifo	aurora_in_fifo
input_fifo	processor_in_fifo
clk_cross_fifo_ila	ila_clk_cross_fifo

Detailed Description

Definition at line 61 of file jfex_test_fifo_2.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/jfex_test_fifo_2.vhd