ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

Back to ROD documentation
jfex_test_fifo_2.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10.01.2022 16:30:58
6 -- Design Name:
7 -- Module Name: input_buffer_4k - RTL
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 --dummy mod --
21 
22 
23 library IEEE;
24 use IEEE.STD_LOGIC_1164.ALL;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx leaf cells in this code.
32 --library UNISIM;
33 --use UNISIM.VComponents.all;
34 
35 entity jfex_test_fifo_2 is
36  Port (
37  m_aclk : IN STD_LOGIC;
38  s_aclk : IN STD_LOGIC;
39  s_aresetn : IN STD_LOGIC;
40  s_axis_tvalid : IN STD_LOGIC;
41  s_axis_tready : OUT STD_LOGIC;
42  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
43  s_axis_tlast : IN STD_LOGIC;
44  s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45  m_axis_tvalid : OUT STD_LOGIC;
46  m_axis_tready : IN STD_LOGIC;
47  m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
48  m_axis_tlast : OUT STD_LOGIC;
49  m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
50  axis_wr_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
51  axis_rd_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
52  timeout_err : in std_logic
53 
54  );
55 
56 
57 
58 
59 end jfex_test_fifo_2;
60 
61 architecture RTL of jfex_test_fifo_2 is
62 
63 
64 
65 COMPONENT aurora_in_fifo
66  PORT (
67  wr_rst_busy : OUT STD_LOGIC;
68  rd_rst_busy : OUT STD_LOGIC;
69  m_aclk : IN STD_LOGIC;
70  s_aclk : IN STD_LOGIC;
71  s_aresetn : IN STD_LOGIC;
72  s_axis_tvalid : IN STD_LOGIC;
73  s_axis_tready : OUT STD_LOGIC;
74  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
75  s_axis_tlast : IN STD_LOGIC;
76  s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
77  m_axis_tvalid : OUT STD_LOGIC;
78  m_axis_tready : IN STD_LOGIC;
79  m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
80  m_axis_tlast : OUT STD_LOGIC;
81  m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82  axis_wr_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
83  axis_rd_data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
84  );
85 END COMPONENT;
86 
87 COMPONENT processor_in_fifo
88  PORT (
89  wr_rst_busy : OUT STD_LOGIC;
90  rd_rst_busy : OUT STD_LOGIC;
91  s_aclk : IN STD_LOGIC;
92  s_aresetn : IN STD_LOGIC;
93  s_axis_tvalid : IN STD_LOGIC;
94  s_axis_tready : OUT STD_LOGIC;
95  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
96  s_axis_tlast : IN STD_LOGIC;
97  s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98  m_axis_tvalid : OUT STD_LOGIC;
99  m_axis_tready : IN STD_LOGIC;
100  m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
101  m_axis_tlast : OUT STD_LOGIC;
102  m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
103  axis_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
104  );
105 END COMPONENT;
106 
107 --component fifo_timer is
108 -- Port (
109 -- aurora_clock : in STD_LOGIC;
110 -- pp_clock : in STD_LOGIC;
111 -- timer : out STD_LOGIC_VECTOR (31 downto 0);
112 -- s_axis_tvalid : in STD_LOGIC;
113 -- s_axis_tlast : in STD_LOGIC;
114 -- s_user_firstcyc : in STD_LOGIC;
115 -- m_axis_tvalid : in STD_LOGIC;
116 -- m_axis_tlast : in STD_LOGIC;
117 -- start_timer : out STD_LOGIC;
118 -- stop_timer : out STD_LOGIC;
119 -- run_timer : out STD_LOGIC;
120 -- packet_count : out STD_LOGIC_VECTOR (7 downto 0);
121 -- reset : in STD_LOGIC
122 -- );
123 --end component;
124 
125 --dummy comment
126 
127 COMPONENT ila_input_fifo
128 PORT (
129  clk : IN STD_LOGIC;
130  probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
131  probe1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
132  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
133  probe3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
134  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
135  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
136  probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
137  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
138  probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
139  probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
140  probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
141  probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
142  probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
143  probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
144  probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
145  probe15 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
146  probe16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
147  probe17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
148  probe18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
149 
150 
151 );
152 END COMPONENT ;
153 
154  COMPONENT ila_clk_cross_fifo
155 PORT (
156  clk : IN STD_LOGIC;
157  probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
158  probe1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
159  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
160  probe3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
161  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
162  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
163  probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
164  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
165  probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
166  probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
167  probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
168  probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
169  probe12 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
170  probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
171  probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
172  probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
173 
174 
175 );
176 END COMPONENT ;
177 
178 signal mid_fifo_tvalid : std_logic;
179 signal mid_fifo_tready : std_logic;
180 signal mid_fifo_tdata : std_logic_vector(63 downto 0);
181 signal mid_fifo_tlast : std_logic;
182 signal mid_fifo_tuser : std_logic_vector(3 downto 0);
183 signal axis_data_count_i : std_logic_vector(31 downto 0);
184 signal axis_data_count : std_logic_vector(31 downto 0);
185 signal s_areset : std_logic;
186 signal timer : std_logic_vector(31 downto 0);
187 signal mid_fifo_wr_data_count : std_logic_vector(9 downto 0);
188 signal mid_fifo_rd_data_count : std_logic_vector(9 downto 0);
189 signal s_axis_tready_i : std_logic;
190 signal start_timer : STD_LOGIC;
191 signal stop_timer : STD_LOGIC;
192 signal run_timer : STD_LOGIC;
193 signal packet_count : STD_LOGIC_VECTOR (7 downto 0);
194 signal m_axis_tvalid_i : STD_LOGIC;
195 signal m_axis_tlast_i : STD_LOGIC;
196 signal m_axis_tdata_i : STD_LOGIC_VECTOR (63 downto 0);
197 signal m_axis_tuser_i : STD_LOGIC_VECTOR (3 downto 0);
198 signal timeout_err_reg : STD_LOGIC;
199 signal s_axis_tvalid_safe : STD_LOGIC;
200 signal mid_fifo_tvalid_safe : STD_LOGIC;
201 signal m_axis_tready_safe : STD_LOGIC;
202 signal clk_cross_wr_rst_busy : STD_LOGIC;
203 signal input_wr_rst_busy : STD_LOGIC;
204 
205 begin
206 
207 
208 clk_cross_fifo : aurora_in_fifo
209 PORT MAP (
210  wr_rst_busy => clk_cross_wr_rst_busy, --open,
211  rd_rst_busy => open,
212  m_aclk => m_aclk,
213  s_aclk => s_aclk,
214  s_aresetn => s_aresetn,
215  s_axis_tvalid => s_axis_tvalid_safe, --s_axis_tvalid,
216  s_axis_tready => s_axis_tready_i,
217  s_axis_tdata => s_axis_tdata,
218  s_axis_tlast => s_axis_tlast,
219  s_axis_tuser => s_axis_tuser,
220 -- s_axis_tuser(0) => first_cyc,
221 -- s_axis_tuser(1) => pipe_m_axis_tlast,
222 -- s_axis_tuser(2) => s_crc_error,
223 -- s_axis_tuser(3) => pipe_m_comb_error,
224  m_axis_tvalid => mid_fifo_tvalid,
225  m_axis_tready => '1', --mid_fifo_tready,
226  m_axis_tdata => mid_fifo_tdata,
227  m_axis_tlast => mid_fifo_tlast,
228  m_axis_tuser => mid_fifo_tuser,
229  axis_wr_data_count => open, --mid_fifo_wr_data_count,
230  axis_rd_data_count => open --mid_fifo_rd_data_count
231 );
232 
233 s_axis_tvalid_safe <= s_axis_tvalid and not clk_cross_wr_rst_busy;
234 s_axis_tready <= '1'; --s_axis_tready_i;
235 
236 input_fifo : processor_in_fifo
237 PORT MAP (
238  wr_rst_busy => input_wr_rst_busy, --open,
239  rd_rst_busy => open,
240  s_aclk => m_aclk,
241  s_aresetn => s_aresetn,
242  s_axis_tvalid => mid_fifo_tvalid_safe, --mid_fifo_tvalid,
243  s_axis_tready => open, --mid_fifo_tready,
244  s_axis_tdata => mid_fifo_tdata,
245  s_axis_tlast => mid_fifo_tlast,
246  s_axis_tuser => mid_fifo_tuser,
247  m_axis_tvalid => m_axis_tvalid_i,
248  m_axis_tready => m_axis_tready_safe, --m_axis_tready,
249  m_axis_tdata => m_axis_tdata_i,
250  m_axis_tlast => m_axis_tlast_i,
251  m_axis_tuser => m_axis_tuser_i,
252  axis_data_count => axis_data_count_i(11 downto 0)
253 );
254 mid_fifo_tvalid_safe <= mid_fifo_tvalid and not input_wr_rst_busy;
255 m_axis_tready_safe <= m_axis_tready or input_wr_rst_busy;
256 axis_data_count <= x"0000" & "0000" & axis_data_count_i(11 downto 0);
257 
258 axis_rd_data_count <= axis_data_count;
259 axis_wr_data_count <= axis_data_count;
260 
261 --clk_cross_fifo_timer : fifo_timer
262 --Port Map (
263 -- aurora_clock => s_aclk,
264 -- pp_clock => m_aclk,
265 -- timer => timer,
266 -- s_axis_tvalid => s_axis_tvalid,
267 ---- s_axis_tvalid => mid_fifo_tvalid,
268 ---- s_axis_tlast => s_axis_tlast,
269 -- s_axis_tlast => mid_fifo_tlast,
270 -- s_user_firstcyc => s_axis_tuser(0),
271 ---- s_user_firstcyc => mid_fifo_tuser(0),
272 -- m_axis_tvalid => mid_fifo_tvalid,
273 -- m_axis_tlast => mid_fifo_tlast,
274 -- start_timer => start_timer,
275 -- stop_timer => stop_timer,
276 -- run_timer => run_timer,
277 -- packet_count => packet_count,
278 -- reset => s_areset
279 
280 -- );
281 
282 s_areset <= not (s_aresetn);
283 
284 clk_cross_fifo_ila : ila_clk_cross_fifo
285 PORT MAP (
286  clk => m_aclk,
287  probe0 => mid_fifo_tdata, --64
288  probe1 => mid_fifo_rd_data_count, --
289  probe2(0) => timeout_err_reg,
290  probe3 => mid_fifo_tuser,
291  probe4(0) => s_aresetn,
292  probe5(0) => '0', --s_axis_tvalid,
293  probe6(0) => '0', --s_axis_tlast,
294  probe7(0) => mid_fifo_tvalid,
295  probe8(0) => mid_fifo_tlast,
296  probe9(0) => '0', --mid_fifo_tready,
297  probe10(0) => m_axis_tready,
298  probe11(0) => '0', --s_axis_tready_i,
299  probe12 => m_axis_tdata_i(63 downto 56), --packet_count,
300  probe13(0) => m_axis_tvalid_i,
301  probe14(0) => m_axis_tlast_i,
302  probe15(0) => m_axis_tuser_i(0)
303 
304 );
305 
306 m_axis_tuser <= m_axis_tuser_i;
307 m_axis_tdata <= m_axis_tdata_i;
308 m_axis_tvalid <= m_axis_tvalid_i;
309 m_axis_tlast <= m_axis_tlast_i;
310 
311 process (m_aclk) begin
312  if rising_edge (m_aclk) then
313  timeout_err_reg <= timeout_err;
314  end if;
315 end process;
316 
317 
318 
319 end RTL;
320 
jfex_test_fifo_2.RTL
Definition: jfex_test_fifo_2.vhd:61
jfex_test_fifo_2
Definition: jfex_test_fifo_2.vhd:35
Generated on Sat Dec 14 2024 13:33:14 for ROD firmware by   doxygen 1.9.1