ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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ufc_rx Entity Reference
Inheritance diagram for ufc_rx:
channel_fifo channel_fifo_p2 input_fifos input_fifos_p2 packet_processor rod_top top_rod_efex top_rod_jfex

Entities

RTL  architecture
 

Libraries

IEEE 

Use Clauses

STD_LOGIC_1164 

Ports

clock   in   STD_LOGIC
reset   in   STD_LOGIC
axi_ufc_rx_tvalid   in   STD_LOGIC
axi_ufc_rx_tlast   in   STD_LOGIC
axi_ufc_rx_tdata   in   STD_LOGIC_Vector ( 15 downto 0 )
ufc_message   out   STD_LOGIC_Vector ( 7 downto 0 )
ufc_parity_error   out   STD_LOGIC
ufc_parity_disable   out   std_logic
ufc_channel_Busy   out   STD_LOGIC

Detailed Description

Definition at line 54 of file ufc_rx.vhd.


The documentation for this class was generated from the following file: