ufc_rx.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 11.05.2020 19:53:07
-- Design Name: 
-- Module Name: ufc_rx - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
 
--The incoming data uses an odd parity scheme which operates on 3 data bits and adds one parity bit on the left.(MSB) 
--Each word has six data bits plus two parity bits 
--There are two copies of the 8-bit data+parity.   The controller should take one without a parity error if possible 
 
--ipbus bits 
 
--parity error counter r
--six sticky bits to record the source of the busy signal 
--reset for all of the above in a separate register 
 
--bits to determine which output the busy is routed to? 
--tob0, bulk0, bulk1, bulk2 
 
 
 
 
 
 
 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ufc_rx is
    Port ( clock               : in STD_LOGIC;
           reset               : in STD_LOGIC;
           axi_ufc_rx_tvalid   : in STD_LOGIC;
           axi_ufc_rx_tlast    : in STD_LOGIC; 
           axi_ufc_rx_tdata    : in STD_LOGIC_Vector(15 downto 0);
           
           ufc_message             : out STD_LOGIC_Vector(7 downto 0);
           ufc_parity_error        : out STD_LOGIC;
           ufc_parity_disable      : out std_logic;
           ufc_channel_Busy        : out STD_LOGIC
                     
           );
end ufc_rx;
 
architecture RTL of ufc_rx is
 
signal  data_cap       :  STD_LOGIC_Vector(15 downto 0);        
signal  message_i        :  STD_LOGIC_Vector(7 downto 0);   
--signal  message_1       :  STD_LOGIC_Vector(7 downto 0);
 
signal  parity_0_0        :  STD_LOGIC;   --message 0 parity on group 0 
signal  parity_0_1        :  STD_LOGIC;   --message 0 parity on group 1
signal  parity_1_0        :  STD_LOGIC;   --message 1 parity on group 0 
signal  parity_1_1        :  STD_LOGIC;   --message 1 parity on group 1 
 
signal  tlast_delay       :  STD_LOGIC;
signal  parity_error_i    :  STD_LOGIC;
 
signal axi_ufc_tdata_1    :  STD_LOGIC_Vector(15 downto 0);
signal axi_ufc_tvalid_1   :  STD_LOGIC;
signal axi_ufc_tlast_1    :  STD_LOGIC;
 
signal axi_ufc_tdata_2    :  STD_LOGIC_Vector(15 downto 0);
signal axi_ufc_tvalid_2   :  STD_LOGIC;
signal axi_ufc_tlast_2    :  STD_LOGIC;
 
signal axi_ufc_tdata_3    :  STD_LOGIC_Vector(15 downto 0);
signal axi_ufc_tvalid_3   :  STD_LOGIC;
signal axi_ufc_tlast_3    :  STD_LOGIC;
 
 
 
begin
 
----first pipeline stage-----
process (clock) begin
   if rising_edge (clock) then
     axi_ufc_tdata_1  <= axi_ufc_rx_tdata; 
     if (reset = '1')  then 
         axi_ufc_tvalid_1 <= '0'; 
         axi_ufc_tlast_1  <= '0'; 
     else 
        axi_ufc_tvalid_1 <= axi_ufc_rx_tvalid; 
        axi_ufc_tlast_1  <= axi_ufc_rx_tlast; 
     end if; 
   end if;   
end process; 
 
----second pipeline stage-----
process (clock) begin
   if rising_edge (clock) then
     axi_ufc_tdata_2  <= axi_ufc_tdata_1; 
     if (reset = '1')  then 
         axi_ufc_tvalid_2 <= '0'; 
         axi_ufc_tlast_2  <= '0'; 
     else 
        axi_ufc_tvalid_2 <= axi_ufc_tvalid_1; 
        axi_ufc_tlast_2  <= axi_ufc_tlast_1; 
     end if; 
   end if;   
end process;
 
----third pipeline stage-----
process (clock) begin
   if rising_edge (clock) then
     axi_ufc_tdata_3  <= axi_ufc_tdata_2; 
     if (reset = '1')  then 
         axi_ufc_tvalid_3 <= '0'; 
         axi_ufc_tlast_3  <= '0'; 
     else 
        axi_ufc_tvalid_3 <= axi_ufc_tvalid_2; 
        axi_ufc_tlast_3  <= axi_ufc_tlast_2; 
     end if; 
   end if;   
end process;
 
 
 
--data capture register 
process (clock) begin 
   if rising_edge (clock) then 
      if reset = '1' then 
         data_cap <= x"0000";
      elsif (axi_ufc_tvalid_3 = '1' and axi_ufc_tlast_3 = '1') then 
         data_cap <= axi_ufc_tdata_3; 
      else  data_cap <= data_cap;   
      end if;
    end if;
end process;
 
parity_0_0 <=  data_cap(3) xor data_cap(2) xor data_cap(1) xor data_cap(0);
parity_0_1 <=  data_cap(7) xor data_cap(6) xor data_cap(5) xor data_cap(4);
parity_1_0 <=  data_cap(11) xor data_cap(10) xor data_cap(9) xor data_cap(8);
parity_1_1 <=  data_cap(15) xor data_cap(14) xor data_cap(13) xor data_cap(12);
 
 
--capture the 16-bit raw ufc data
 
--process (clock) begin 
--   if rising_edge (clock) then 
--      if reset = '1' then 
--         data_cap <= x"0000";
--      elsif (axi_ufc_rx_tvalid = '1' and axi_ufc_rx_tlast = '1') then 
--         data_cap <= axi_ufc_rx_tdata; 
--      else  data_cap <= data_cap;   
--      end if;
--    end if;
--end process;
 
 
 
process (clock) begin 
   if rising_edge (clock) then 
      if reset = '1' then 
         message_i(3 downto 0) <= x"0";
      elsif (parity_0_0 = '1') or (ufc_parity_disable = '1') then 
         message_i(3 downto 0) <= data_cap(3 downto 0); 
      elsif (parity_0_0 = '0') and (parity_1_0 = '1') then 
         message_i(3 downto 0) <= data_cap(11 downto 8);          
      else  message_i(3 downto 0) <= x"0";   
      end if;
    end if;
end process;
 
process (clock) begin 
   if rising_edge (clock) then 
      if reset = '1' then 
         message_i(7 downto 4) <= x"0";
      elsif (parity_0_1 = '1') or (ufc_parity_disable = '1')then 
         message_i(7 downto 4) <= data_cap(7 downto 4); 
      elsif (parity_0_1 = '0') and (parity_1_1 = '1') then 
         message_i(7 downto 4) <= data_cap(15 downto 12);          
      else  message_i(7 downto 4) <= x"0";   
      end if;
    end if;
end process;
 
 
 
process (clock) begin 
   if rising_edge (clock) then 
      if reset = '1' then 
         tlast_delay <= '0'; 
      else  
         tlast_delay <= axi_ufc_tvalid_3 and axi_ufc_tlast_3; 
      end if;
    end if;
end process;
 
--parity error is a single cycle pulse one cycle after the message has been received
 
process (clock) begin 
   if rising_edge (clock) then 
      if (reset = '1') or (tlast_delay = '0') then 
         parity_error_i <= '0'; 
      elsif (tlast_delay = '1') then 
         parity_error_i <= ((not parity_0_0) or (not parity_0_1) or (not parity_1_0)or (not parity_1_1)) ;
      else   parity_error_i <=  parity_error_i;  
      end if;
    end if;
end process;
 
ufc_parity_error <= parity_error_i;
--parity_error <= tlast_delay and ((not parity_0_0) or (not parity_0_1) or (not parity_1_0)or (not parity_1_1)) ;
 
ufc_channel_Busy <= message_i(6) or message_i(5) or message_i(4) or  message_i(2) or message_i(1) or message_i(0);
 
ufc_message <= message_i;
 
end RTL;