RTL Architecture Reference

Processes
PROCESS_340	( clock )
PROCESS_341	( clock )
PROCESS_342	( clock )
PROCESS_343	( clock )
PROCESS_344	( clock )
PROCESS_345	( clock )
PROCESS_346	( clock )
PROCESS_347	( clock )

Signals
data_cap	STD_LOGIC_Vector ( 15 downto 0 )
message_i	STD_LOGIC_Vector ( 7 downto 0 )
parity_0_0	STD_LOGIC
parity_0_1	STD_LOGIC
parity_1_0	STD_LOGIC
parity_1_1	STD_LOGIC
tlast_delay	STD_LOGIC
parity_error_i	STD_LOGIC
axi_ufc_tdata_1	STD_LOGIC_Vector ( 15 downto 0 )
axi_ufc_tvalid_1	STD_LOGIC
axi_ufc_tlast_1	STD_LOGIC
axi_ufc_tdata_2	STD_LOGIC_Vector ( 15 downto 0 )
axi_ufc_tvalid_2	STD_LOGIC
axi_ufc_tlast_2	STD_LOGIC
axi_ufc_tdata_3	STD_LOGIC_Vector ( 15 downto 0 )
axi_ufc_tvalid_3	STD_LOGIC
axi_ufc_tlast_3	STD_LOGIC

Detailed Description

Definition at line 69 of file ufc_rx.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/ufc_rx.vhd