fex_chan_regs Entity Reference

Inheritance diagram for fex_chan_regs:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
STD_LOGIC_UNSIGNED
ipbus
ipbus_decode_L1CaloHubRodChannel

Generics
COUNTER_WIDTH	integer := 5
jfex	integer := 0

Ports
ipb_clk	in	std_logic
ipb_rst	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
pp_clock	in	std_logic
time_count	in	STD_LOGIC_VECTOR ( 31 downto 0 )
aurora_chan_stat	in	STD_LOGIC_VECTOR ( 31 downto 0 )
tob_fifo_level	in	STD_LOGIC_VECTOR ( 15 downto 0 )
tob_fifo_busy_threshold	in	STD_LOGIC_VECTOR ( 15 downto 0 )
bulk_fifo_level	in	STD_LOGIC_VECTOR ( 15 downto 0 )
bulk_fifo_busy_threshold	in	STD_LOGIC_VECTOR ( 15 downto 0 )
tob_fifo_xoff_threshold	in	STD_LOGIC_VECTOR ( 15 downto 0 )
bulk_fifo_xoff_threshold	in	STD_LOGIC_VECTOR ( 15 downto 0 )
hdr_crc_tag	in	std_logic
pkt_len_violation	in	std_logic
aurora_channel_control	out	STD_LOGIC_VECTOR ( 31 downto 0 )
chan_disable	in	std_logic
aurora_user_clk	in	std_logic
init_clk	in	std_logic
clk_160	in	std_logic
rt_clk	in	std_logic
bp_reg_reset	in	std_logic
master_reset	in	std_logic
ufc_message	in	STD_LOGIC_Vector ( 7 downto 0 )
ufc_parity_error	in	STD_LOGIC
ufc_channel_Busy	in	STD_LOGIC
ufc_parity_disable	out	std_logic
channel_busy	out	std_logic
L1A	in	std_logic
s_tvalid	in	std_logic
repeat_l1id_counter	in	STD_LOGIC_vector ( 31 downto 0 )
repeat_l1id_counter_reset	out	STD_LOGIC
packets_read_counter	in	STD_LOGIC_vector ( 31 downto 0 )
packets_read_counter_reset	out	STD_LOGIC

Detailed Description

Definition at line 46 of file fex_chan_regs.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/fex_chan_regs.vhd