ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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fex_chan_regs.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15.03.2019 17:49:22
6 -- Design Name:
7 -- Module Name: jfex_chan_regs - jfex_chan_regs
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 --Aurora Channel Control bus
20 --0: Channel Reset
21 --1: Channel Disable
22 --2: Channel Status Reset
23 
24 --Aurora chan stat
25 --0:
26 ----------------------------------------------------------------------------------
27 
28 
29 library IEEE;
30 use IEEE.STD_LOGIC_1164.ALL;
31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
32 use work.ipbus.all;
33 --use work.ipbus_decode_jfex_chan_regs.all;
34 --use work.ipbus_decode_rod_input_chan.all;
35 use work.ipbus_decode_L1CaloHubRodChannel.all;
36 
37 -- Uncomment the following library declaration if using
38 -- arithmetic functions with Signed or Unsigned values
39 --use IEEE.NUMERIC_STD.ALL;
40 
41 -- Uncomment the following library declaration if instantiating
42 -- any Xilinx leaf cells in this code.
43 --library UNISIM;
44 --use UNISIM.VComponents.all;
45 
46 entity fex_chan_regs is
47  generic (
48  COUNTER_WIDTH : integer := 5;
49  jfex : integer := 0
50  );
51  port(
52  ipb_clk: in std_logic;
53  ipb_rst: in std_logic;
54  ipb_in: in ipb_wbus;
55  ipb_out: out ipb_rbus;
56 
57  pp_clock : in std_logic;
58 
59  time_count : in STD_LOGIC_VECTOR (31 downto 0); --synchronous to the pp_clock
60  aurora_chan_stat : in STD_LOGIC_VECTOR (31 downto 0);
61  tob_fifo_level: in STD_LOGIC_VECTOR (15 downto 0); --synchronous to the pp_clock
62  tob_fifo_busy_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
63  bulk_fifo_level: in STD_LOGIC_VECTOR (15 downto 0); --synchronous to the pp_clock
64  bulk_fifo_busy_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
65  tob_fifo_xoff_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
66  bulk_fifo_xoff_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
67 
68  hdr_crc_tag : in std_logic;
69  pkt_len_violation : in std_logic;
70 
71  aurora_channel_control : out STD_LOGIC_VECTOR (31 downto 0); --synchronous to ipb_clk
72  chan_disable : in std_logic;
73 
74  aurora_user_clk : in std_logic;
75  init_clk : in std_logic;
76  clk_160 : in std_logic;
77  rt_clk : in std_logic;
78  bp_reg_reset : in std_logic;
79  master_reset : in std_logic;
80 
81  --ufc message axi bus --------------------------------------
82 -- s_axi_ufc_rx_tdata : in std_logic_vector(63 downto 0);
83 -- s_axi_ufc_rx_tvalid : in std_logic;
84  -- s_axi_ufc_rx_tlast : in std_logic
85  ufc_message : in STD_LOGIC_Vector(7 downto 0);
86  ufc_parity_error : in STD_LOGIC;
87  ufc_channel_Busy : in STD_LOGIC;
88  ufc_parity_disable : out std_logic;
89  channel_busy : out std_logic;
90 -- channel_xoff : out std_logic;
91 -- tob_fifo_xoff : out std_logic;
92 -- bulk_fifo_xoff : out std_logic;
93 
94  L1A : in std_logic;
95  s_tvalid : in std_logic;
96 
97  repeat_l1id_counter : in STD_LOGIC_vector(31 downto 0);
98  repeat_l1id_counter_reset : out STD_LOGIC;
99  packets_read_counter : in STD_LOGIC_vector(31 downto 0);
100  packets_read_counter_reset: out STD_LOGIC
101  );
102 
103 end fex_chan_regs;
104 
105 -------------aurora status/control bus definitions-----------------------
106 --aurora_chan_stat(0) = channel up
107 --aurora_chan_stat(1) = Rx reset Done
108 --aurora_chan_stat(2) = cpll locked
109 --aurora_chan_stat(3) = 0 (not used)
110 --aurora_chan_stat(7 downto 4)) = lane up
111 --aurora_chan_stat(8) = hard error
112 --aurora_chan_stat(9) = soft error
113 --aurora_chan_stat(10) = frame error
114 --aurora_chan_stat(11) = protocol error
115 
116 
117 --aurora_channel_control(0) = channel reset pulse (used to trigger timer in backplane)
118 
119 --aurora_channel_control(1) = clear channel error counters (pulse)
120 --aurora_channel_control(2) = channel disable
121 --aurora_channel_control(3) = TOB fifo reset (including control state machines)
122 --aurora_channel_control(4) = Bulk fifo reset (including control state machines)
123 --aurora_channel_control(6) = TOB fifo xoff
124 --aurora_channel_control(7) = Bulk fifo xoff
125 
126 
127 --aurora_channel_control(29) = fex_reset_out (feeds the readout_control reset bit for the channel)
128 --aurora_channel_control(30) = Aurora reset (timed)
129 --aurora_channel_control(31) = Aurora channel GT reset (timed)
130 
131 ---------------------------------------------------------------------------
132 
133 architecture RTL of fex_chan_regs is
134 
135 component pulse_stretch is
136  generic (
137  COUNTER_WIDTH : integer := 5
138  );
139  Port (
140  clock : in STD_LOGIC;
141  reset : in STD_LOGIC;
142  pulse_in : in STD_LOGIC;
143  pulse_out : out STD_LOGIC
144 
145  );
146 end component;
147 
148 component channel_init
149  generic (
150  jfex : integer := 0
151  );
152  Port (
153  init_clk : in STD_LOGIC;
154  chan_reg_reset : in STD_LOGIC;
155  bp_reg_reset : in STD_LOGIC;
156  master_reset : in STD_LOGIC;
157  channel_up : in STD_LOGIC;
158  error_counter_reset : in STD_LOGIC;
159  aurora_reset_out : out STD_LOGIC;
160  GT_reset : out STD_LOGIC;
161  fex_reset : out STD_LOGIC;
162  self_reset_count : out std_logic_vector(31 downto 0);
163  chan_up_time : out std_logic_vector(31 downto 0);
164  channel_down_auto_reset_disable : in std_logic
165  );
166 
167 end component;
168 
169 COMPONENT ila_self_reset
170 
171 PORT (
172  clk : IN STD_LOGIC;
173  probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
174  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
175  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
176  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
177  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
178  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
179  probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
180  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
181  probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
182  probe9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
183  probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
184  probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
185  probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
186 );
187 END COMPONENT ;
188 
189 component edge_error_counter
190  generic(
191  cwidth: positive := 4
192  );
193  Port (
194  clock : in STD_LOGIC;
195  counter_reset : in STD_LOGIC;
196  system_reset : in STD_LOGIC;
197  error : in STD_LOGIC;
198  error_count : out STD_LOGIC_VECTOR(cwidth-1 downto 0)
199 
200  );
201 end component;
202 
203 component tob_rx_timer
204  Port (
205  pp_clock : in STD_LOGIC;
206  L1A : in STD_LOGIC;
207  s_tvalid : in STD_LOGIC;
208  reset : in STD_LOGIC;
209  tob_rx_time : out std_logic_vector(15 downto 0);
210  tob_rx_time_max : out std_logic_vector(15 downto 0)
211  );
212 
213 end component;
214 
215 --component ufc_rx
216 -- Port ( clock : in STD_LOGIC;
217 -- reset : in STD_LOGIC;
218 -- axi_ufc_rx_tvalid : in STD_LOGIC;
219 -- axi_ufc_rx_tlast : in STD_LOGIC;
220 -- axi_ufc_rx_tdata : in STD_LOGIC_Vector(15 downto 0);
221 --
222 -- message : out STD_LOGIC_Vector(7 downto 0);
223 -- parity_error : out STD_LOGIC;
224 -- channel_Busy : out STD_LOGIC
225  -- );
226 ---end component;
227 
228  signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
229  signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
230 -- signal stat_reg_out : std_logic_vector (31 downto 0);
231  signal tob_fifo_control : std_logic_vector (31 downto 0);
232  signal Tob_fifo_status : std_logic_vector (31 downto 0);
233  signal Tob_fifo_fill_level : std_logic_vector (31 downto 0);
234  signal Tob_fifo_busy_Count : std_logic_vector (31 downto 0);
235  signal Tob_fifo_xoff_count : std_logic_vector (31 downto 0);
236 
237  signal bulk_fifo_control : std_logic_vector (31 downto 0);
238  signal bulk_fifo_status : std_logic_vector (31 downto 0);
239  signal bulk_fifo_fill_level : std_logic_vector (31 downto 0);
240  signal bulk_fifo_busy_Count : std_logic_vector (31 downto 0);
241  signal bulk_fifo_xoff_count : std_logic_vector (31 downto 0);
242  signal Aurora_channel_status : std_logic_vector (31 downto 0);
243  signal data_integrity_status : std_logic_vector (31 downto 0);
244  signal hard_error_count : std_logic_vector (3 downto 0);
245  signal soft_error_count : std_logic_vector (3 downto 0);
246  signal frame_error_count : std_logic_vector (3 downto 0);
247  signal protocol_error_count : std_logic_vector (3 downto 0);
248  signal header_crc_error_count : std_logic_vector (3 downto 0);
249  signal trailer_crc_error_count: std_logic_vector (3 downto 0);
250  signal odd_word_error_count : std_logic_vector (3 downto 0);
251  signal aurora_channel_control_i : std_logic_vector (31 downto 0);
252  signal error_counter_reset : std_logic;
253 
254 
255  signal tob_counter_reset : std_logic;
256  signal bulk_busy_counter_reset : std_logic;
257  signal bulk_xoff_counter_reset : std_logic;
258  signal tfifo_xoff_tcount : std_logic_vector (31 downto 0);
259 
260  signal channel_control_reset : std_logic;
261  signal channel_control_stb : std_logic;
262  signal channel_reset_pulse : std_logic;
263 
264  signal tob_fifo_rst_rst : std_logic;
265  signal tob_fifo_rst_stb : std_logic;
266  signal tob_fifo_reset : std_logic_vector (31 downto 0);
267 
268  signal bulk_fifo_rst_rst : std_logic;
269  signal bulk_fifo_rst_stb : std_logic;
270  signal bulk_fifo_reset : std_logic_vector (31 downto 0);
271 
272  signal aurora_reset_disable_i : std_logic_vector (31 downto 0);
273  signal channel_down_auto_reset_disable : std_logic;
274  signal pkt_len_violation_auto_reset_disable : std_logic;
275 
276  signal chan_reset_trig : std_logic; --stretched reset pulse generated by setting reg bit
277  signal channel_up : std_logic;
278 
279  signal crc_error : std_logic;
280  signal prev_hdr_crc_tag : std_logic;
281 
282  signal frame_err : std_logic;
283 
284  signal tob_watermark_reset : std_logic;
285  signal tob_watermark : std_logic_vector (15 downto 0);
286  signal bulk_watermark_reset : std_logic;
287  signal bulk_watermark : std_logic_vector (15 downto 0);
288  signal pkt_maxlen_error_count : std_logic_vector (3 downto 0);
289 
290  --signal ufc_message : std_logic_vector (7 downto 0);
291  --signal ufc_parity_error : std_logic;
292  signal ufc_channel_Busy_i : std_logic;
293  signal ufc_reset : std_logic;
294 
295 signal ufc_timer_0 : std_logic_vector(33 downto 0);
296 signal ufc_timer_1 : std_logic_vector(33 downto 0);
297 signal ufc_timer_2 : std_logic_vector(33 downto 0);
298 signal ufc_timer_3 : std_logic_vector(33 downto 0);
299 signal ufc_timer_4 : std_logic_vector(33 downto 0);
300 signal ufc_timer_5 : std_logic_vector(33 downto 0);
301 
302 signal ufc_timer_reset : std_logic_vector(31 downto 0);
303 signal t_reset : std_logic_vector(31 downto 0);
304 
305 signal ufc_status : std_logic_vector(31 downto 0);
306 signal ufc_busy_control : std_logic_vector(31 downto 0);
307 
308 signal ufc_parity_count : std_logic_vector(31 downto 0);
309 signal ufc_timer_rst_rst : std_logic;
310 signal ufc_timer_rst_stb : std_logic;
311 
312 signal tob_fifo_busy : std_logic;
313 signal tob_fifo_xoff_i : std_logic;
314 signal bulk_fifo_busy : std_logic;
315 signal bulk_fifo_xoff_i : std_logic;
316 signal tob_fifo_busy_enable : std_logic;
317 signal tob_fifo_xoff_enable : std_logic;
318 signal tob_fifo_force_busy : std_logic;
319 signal bulk_fifo_busy_enable : std_logic;
320 signal bulk_fifo_xoff_enable : std_logic;
321 signal bulk_fifo_force_busy : std_logic;
322 
323 
324 signal tob_fifo_force_xoff : std_logic;
325 signal bulk_fifo_force_xoff : std_logic;
326 signal aurora_self_reset_count : std_logic_vector(31 downto 0);
327 signal chan_up_time : std_logic_vector(31 downto 0);
328 
329 signal tob_rx_time : std_logic_vector(15 downto 0);
330 signal tob_rx_time_max : std_logic_vector(15 downto 0);
331 
332 begin
333 -- ipbus address decode
334 
335  fabric: entity work.ipbus_fabric_sel
336  generic map(
337  NSLV => N_SLAVES,
338  SEL_WIDTH => IPBUS_SEL_WIDTH)
339  port map(
340  ipb_in => ipb_in,
341  ipb_out => ipb_out,
342  sel => ipbus_sel_L1CaloHubRodChannel(ipb_in.ipb_addr),
343  ipb_to_slaves => ipbw,
344  ipb_from_slaves => ipbr
345  );
346 
347 --TOB FIFO Control register
348  --bit-0: TOB FIFO busy enable
349  --bit-1: TOB FIFO xoff enable
350 
351 
352 Tob_fifo_control_reg: entity work.ipbus_reg_v
353  port map(
354  clk => ipb_clk,
355  reset => ipb_rst,
356  ipbus_in => ipbw(N_SLV_Tob_fifo_control),
357  ipbus_out => ipbr(N_SLV_Tob_fifo_control),
358  q(0) => tob_fifo_control
359  );
360 tob_fifo_busy_enable <= tob_fifo_control(0);
361 tob_fifo_xoff_enable <= tob_fifo_control(1);
362 tob_fifo_force_busy <= tob_fifo_control(4);
363 tob_fifo_force_xoff <= tob_fifo_control(5);
364 
365 Tob_fifo_reset_reg: entity work.ipbus_reg_v
366  port map(
367  clk => ipb_clk,
368  reset => tob_fifo_rst_rst,
369  ipbus_in => ipbw(N_SLV_Tob_fifo_reset),
370  ipbus_out => ipbr(N_SLV_Tob_fifo_reset),
371  stb(0) => tob_fifo_rst_stb,
372  q(0) => tob_fifo_reset
373  );
374 tob_fifo_rst_rst <= tob_fifo_rst_stb or ipb_rst;
375 
376 aurora_channel_control(3) <= tob_fifo_reset(0);
377 repeat_l1id_counter_reset <= tob_fifo_reset(5);
378 packets_read_counter_reset <= tob_fifo_reset(6);
379 
380  --need to merge fifo resets in with channel control
381 
382 -----------------------------------------------------------------------------------------------
383 Tob_fifo_status_reg: entity work.ipbus_syncreg_v
384  generic map (
385  N_CTRL => 0,
386  N_STAT => 1
387  )
388  port map (
389  clk => ipb_clk,
390  rst => ipb_rst,
391  ipb_in => ipbw(N_SLV_Tob_fifo_status),
392  ipb_out => ipbr(N_SLV_Tob_fifo_status),
393  slv_clk => pp_clock,
394  d(0) => Tob_fifo_status,
395  qmask => (others => (others => '1')),
396  stb => open,
397  rstb => open
398  );
399 
400 --Tob_fifo_status bus
401 -- bit-0: overrun flag
402 -- busy threshold exceeded
403 -- xoff threshold exceeded
404 
405 
406 
407 Tob_fifo_status(0) <= '1' WHEN (tob_fifo_level > x"fff") ELSE '0';
408 Tob_fifo_status(1) <= '1' WHEN (tob_fifo_level > tob_fifo_busy_threshold) ELSE '0';
409 Tob_fifo_status(2) <= '1' WHEN (tob_fifo_level > tob_fifo_xoff_threshold) ELSE '0';
410 
411 ----------------------------------------------------------------------------------------------------------
412 Tob_fifo_fill_level_reg : entity work.ipbus_syncreg_v
413  generic map (
414  N_CTRL => 0,
415  N_STAT => 1
416  )
417  port map (
418  clk => ipb_clk,
419  rst => ipb_rst,
420  ipb_in => ipbw(N_SLV_Tob_fifo_fill_level),
421  ipb_out => ipbr(N_SLV_Tob_fifo_fill_level),
422  slv_clk => pp_clock,
423  d(0) => Tob_fifo_fill_level,
424  qmask => (others => (others => '1')),
425  stb => open,
426  rstb => open
427  );
428 
429 Tob_fifo_fill_level(15 downto 0) <= tob_fifo_level;
430 Tob_fifo_fill_level(31 downto 16) <= tob_watermark;
431 
432 
433 tob_fifo_watermark : entity work.watermark
434  generic map (
435  watermark_width => 16
436  )
437  port map (
438  clock => pp_clock,
439  level => tob_fifo_level,
440  reset => tob_watermark_reset,
441  watermark => tob_watermark
442  );
443 
444 tob_watermark_reset <= (ipb_rst or tob_fifo_reset(3));
445 
446 
447 ----------------------------------------------------------------------------------------------------------------
448 
449 Tob_fifo_busy_Count_reg : entity work.ipbus_syncreg_v
450  generic map (
451  N_CTRL => 0,
452  N_STAT => 1
453  )
454  port map (
455  clk => ipb_clk,
456  rst => ipb_rst,
457  ipb_in => ipbw(N_SLV_Tob_fifo_busy_count),
458  ipb_out => ipbr(N_SLV_Tob_fifo_busy_count),
459  slv_clk => rt_clk, --changed to clk_160 because it will always be 160MHz (pp_clock may change)
460  d(0) => Tob_fifo_busy_count,
461  qmask => (others => (others => '1')),
462  stb => open,
463  rstb => open
464  );
465 
466  tob_fifo_busy_counter: entity work.threshold_counter
467  port map (
468  clock => rt_clk, --changed to clk_40 (pp_clock may change)
469  reset => tob_fifo_reset(1),
470  threshold => tob_fifo_busy_threshold,
471  level => tob_fifo_level,
472  above_count => Tob_fifo_busy_Count,
473  busy => tob_fifo_busy
474  );
475 
476 Tob_fifo_xoff_Count_reg : entity work.ipbus_syncreg_v
477  generic map (
478  N_CTRL => 0,
479  N_STAT => 1
480  )
481  port map (
482  clk => ipb_clk,
483  rst => ipb_rst,
484  ipb_in => ipbw(N_SLV_Tob_fifo_xoff_count),
485  ipb_out => ipbr(N_SLV_Tob_fifo_xoff_count),
486  slv_clk => rt_clk, --changed to clk_160 because it will always be 160MHz (pp_clock may change)
487  d(0) => Tob_fifo_xoff_count,
488  qmask => (others => (others => '1')),
489  stb => open,
490  rstb => open
491  );
492 
493  tob_fifo_xoff_counter: entity work.threshold_counter
494  port map (
495  clock => rt_clk, --changed to clk_160 because it will always be 160MHz (pp_clock may change)
496  reset => tob_fifo_reset(2),
497  threshold => tob_fifo_xoff_threshold,
498  level => tob_fifo_level,
499  above_count => Tob_fifo_xoff_Count,
500  busy => tob_fifo_xoff_i
501  );
502 
503 -----------------------------------------------------------------------------------------------
504 Bulk_fifo_control_reg: entity work.ipbus_reg_v
505  port map(
506  clk => ipb_clk,
507  reset => ipb_rst,
508  ipbus_in => ipbw(N_SLV_bulk_fifo_control),
509  ipbus_out => ipbr(N_SLV_bulk_fifo_control),
510  q(0) => bulk_fifo_control
511  );
512 
513 bulk_fifo_busy_enable <= bulk_fifo_control(0);
514 bulk_fifo_xoff_enable <= bulk_fifo_control(1);
515 bulk_fifo_force_busy <= bulk_fifo_control(4);
516 bulk_fifo_force_xoff <= bulk_fifo_control(5);
517 
518 
519 
520 
521 ---------------------------------------------------------------------------------------
522 bulk_fifo_reset_reg: entity work.ipbus_reg_v
523  port map(
524  clk => ipb_clk,
525  reset => bulk_fifo_rst_rst,
526  ipbus_in => ipbw(N_SLV_bulk_fifo_reset),
527  ipbus_out => ipbr(N_SLV_bulk_fifo_reset),
528  stb(0) => bulk_fifo_rst_stb,
529  q(0) => bulk_fifo_reset
530  );
531 bulk_fifo_rst_rst <= bulk_fifo_rst_stb or ipb_rst;
532 bulk_busy_counter_reset <= bulk_fifo_reset(1);
533 bulk_xoff_counter_reset <= bulk_fifo_reset(2);
534 aurora_channel_control(4) <= bulk_fifo_reset(0);
535 
536 -------------------------------------------------------------------
537 bulk_fifo_status_reg: entity work.ipbus_syncreg_v
538  generic map (
539  N_CTRL => 0,
540  N_STAT => 1
541  )
542  port map (
543  clk => ipb_clk,
544  rst => ipb_rst,
545  ipb_in => ipbw(N_SLV_bulk_fifo_status),
546  ipb_out => ipbr(N_SLV_bulk_fifo_status),
547  slv_clk => pp_clock,
548  d(0) => bulk_fifo_status,
549  qmask => (others => (others => '1')),
550  stb => open,
551  rstb => open
552  );
553 
554 
555 
556 bulk_fifo_status(0) <= '1' WHEN (bulk_fifo_level > x"fff") ELSE '0';
557 bulk_fifo_status(1) <= '1' WHEN (bulk_fifo_level > bulk_fifo_busy_threshold) ELSE '0';
558 bulk_fifo_status(2) <= '1' WHEN (bulk_fifo_level > bulk_fifo_xoff_threshold) ELSE '0';
559 
560 ----------------------------------------------------------------------------------------------------------
561 bulk_fifo_fill_level_reg : entity work.ipbus_syncreg_v
562  generic map (
563  N_CTRL => 0,
564  N_STAT => 1
565  )
566  port map (
567  clk => ipb_clk,
568  rst => ipb_rst,
569  ipb_in => ipbw(N_SLV_bulk_fifo_fill_level),
570  ipb_out => ipbr(N_SLV_bulk_fifo_fill_level),
571  slv_clk => pp_clock,
572  d(0) => bulk_fifo_fill_level,
573  qmask => (others => (others => '1')),
574  stb => open,
575  rstb => open
576  );
577 
578 bulk_fifo_fill_level(15 downto 0) <= bulk_fifo_level;
579 bulk_fifo_fill_level(31 downto 16) <= bulk_watermark;
580 
581 
582 bulk_fifo_watermark : entity work.watermark
583  generic map (
584  watermark_width => 16
585  )
586  port map (
587  clock => pp_clock,
588  level => bulk_fifo_level,
589  reset => bulk_watermark_reset,
590  watermark => bulk_watermark
591  );
592 
593 bulk_watermark_reset <= (ipb_rst or bulk_fifo_reset(3));
594 
595 
596 
597 
598 ----------------------------------------------------------------------------------------------------------------
599 
600 bulk_fifo_busy_Count_reg : entity work.ipbus_syncreg_v
601  generic map (
602  N_CTRL => 0,
603  N_STAT => 1
604  )
605  port map (
606  clk => ipb_clk,
607  rst => ipb_rst,
608  ipb_in => ipbw(N_SLV_bulk_fifo_busy_count),
609  ipb_out => ipbr(N_SLV_bulk_fifo_busy_count),
610  slv_clk => rt_clk, --changed to clk_160 because it will always be 160MHz (pp_clock may change)
611  d(0) => bulk_fifo_busy_count,
612  qmask => (others => (others => '1')),
613  stb => open,
614  rstb => open
615  );
616 
617  bulk_fifo_busy_counter: entity work.threshold_counter
618  port map (
619  clock => rt_clk, --changed to clk_160 because it will always be 160MHz (pp_clock may change)
620  reset => bulk_busy_counter_reset,
621  threshold => bulk_fifo_busy_threshold,
622  level => bulk_fifo_level,
623  above_count => bulk_fifo_busy_Count,
624  busy => bulk_fifo_busy
625  );
626 
627 ---------------------------------------------------------------------------------------
628 bulk_fifo_xoff_Count_reg : entity work.ipbus_syncreg_v
629  generic map (
630  N_CTRL => 0,
631  N_STAT => 1
632  )
633  port map (
634  clk => ipb_clk,
635  rst => ipb_rst,
636  ipb_in => ipbw(N_SLV_bulk_fifo_xoff_count),
637  ipb_out => ipbr(N_SLV_bulk_fifo_xoff_count),
638  slv_clk => rt_clk, --changed to clk_160 because it will always be 160MHz (pp_clock may change)
639  d(0) => bulk_fifo_xoff_count,
640  qmask => (others => (others => '1')),
641  stb => open,
642  rstb => open
643  );
644 
645  bulk_fifo_xoff_counter: entity work.threshold_counter
646  port map (
647 -- clock => pp_clock,
648  clock => rt_clk, --changed to clk_160 because it will always be 160MHz (pp_clock may change)
649  reset => bulk_xoff_counter_reset,
650  threshold => bulk_fifo_xoff_threshold,
651  level => bulk_fifo_level,
652  above_count => bulk_fifo_xoff_Count,
653  busy => bulk_fifo_xoff_i
654  );
655 
656 -----------------------------------------------------------------------------------------------
657 
658 ---------PULSE REGISTER---------------
659 Aurora_channel_control_reg: entity work.ipbus_reg_v
660  port map(
661  clk => ipb_clk,
662  reset => channel_control_reset, --reset pulse in
663  ipbus_in => ipbw(N_SLV_aurora_channel_control),
664  ipbus_out => ipbr(N_SLV_aurora_channel_control),
665  stb(0) => channel_control_stb, --reset pulse out
666  q(0) => aurora_channel_control_i
667  );
668 
669 channel_control_reset <= ipb_rst or channel_control_stb;
670 
671 channel_reset_pulse <= aurora_channel_control_i(0) or (pkt_len_violation and not pkt_len_violation_auto_reset_disable) ;
672 
673 aurora_reset_pulse: pulse_stretch
674  generic map (
675  COUNTER_WIDTH => 5
676  )
677  port map (
678  clock => ipb_clk,
679  reset => ipb_rst,
680 -- pulse_in => aurora_channel_control_i(0),
681  pulse_in => channel_reset_pulse,
682 -- pulse_out => aurora_channel_control(0)
683  pulse_out => chan_reset_trig
684  );
685 
686 
687 aurora_channel_control(1) <= aurora_channel_control_i(1);
688 
689 error_counter_reset <= aurora_channel_control_i(1);
690 -------------------------------------------------------------------------------------
691 Aurora_autoreset_disable: entity work.ipbus_reg_v
692  port map(
693  clk => ipb_clk,
694  reset => ipb_rst,
695  ipbus_in => ipbw(N_SLV_aurora_autoreset_disable),
696  ipbus_out => ipbr(N_SLV_aurora_autoreset_disable),
697  q(0) => aurora_reset_disable_i
698  );
699 
700 channel_down_auto_reset_disable <= aurora_reset_disable_i(0);
701 pkt_len_violation_auto_reset_disable <= aurora_reset_disable_i(1);
702 
703 
704 
705 aurora_channel_control(2) <= chan_disable;
706 
707 
708 
709 --------------------------------------------------------------------------------------------------
710 Aurora_channel_status_reg : entity work.ipbus_syncreg_v
711  generic map (
712  N_CTRL => 0,
713  N_STAT => 1
714  )
715  port map (
716  clk => ipb_clk,
717  rst => ipb_rst,
718  ipb_in => ipbw(N_SLV_Aurora_channel_status),
719  ipb_out => ipbr(N_SLV_Aurora_channel_status),
720  slv_clk => pp_clock,
721  d(0) => Aurora_channel_status,
722  qmask => (others => (others => '1')),
723  stb => open,
724  rstb => open
725  );
726 
727 Aurora_channel_status(0) <= aurora_chan_stat(0); --channel_up
728 Aurora_channel_status(1) <= aurora_chan_stat(1); --Rx reset Done
729 Aurora_channel_status(2) <= aurora_chan_stat(2); --cpll locked
730 Aurora_channel_status(3) <= '0'; --not used
731 Aurora_channel_status(7 downto 4) <= aurora_chan_stat(7 downto 4); --lane up
732 Aurora_channel_status(11 downto 8) <= hard_error_count(3 downto 0);
733 Aurora_channel_status(15 downto 12) <= soft_error_count(3 downto 0);
734 Aurora_channel_status(19 downto 16) <= frame_error_count(3 downto 0);
735 Aurora_channel_status(23 downto 20) <= header_crc_error_count(3 downto 0);
736 Aurora_channel_status(27 downto 24) <= trailer_crc_error_count(3 downto 0);
737 Aurora_channel_status(31 downto 28) <= pkt_maxlen_error_count(3 downto 0);
738 
739 
740 data_integrity_status_reg : entity work.ipbus_syncreg_v
741  generic map (
742  N_CTRL => 0,
743  N_STAT => 1
744  )
745  port map (
746  clk => ipb_clk,
747  rst => ipb_rst,
748  ipb_in => ipbw(N_SLV_data_integrity_status),
749  ipb_out => ipbr(N_SLV_data_integrity_status),
750  slv_clk => pp_clock,
751  d(0) => data_integrity_status,
752  qmask => (others => (others => '1')),
753  stb => open,
754  rstb => open
755  );
756 
757 data_integrity_status(3 downto 0) <= protocol_error_count(3 downto 0);
758 data_integrity_status(7 downto 4) <= odd_word_error_count(3 downto 0);
759 data_integrity_status(31 downto 8) <= x"000000";
760 
761 
762 
763 
764 
765 
766 
767 hard_error_counter: entity work.error_counter
768  port map (
769  clock => pp_clock,
770  counter_reset => error_counter_reset,
771  system_reset => ipb_rst,
772  error => aurora_chan_stat(8),
773  error_count => hard_error_count
774  );
775 
776 soft_error_counter: entity work.error_counter
777  port map (
778  clock => pp_clock,
779  counter_reset => error_counter_reset,
780  system_reset => ipb_rst,
781  error => aurora_chan_stat(9),
782  error_count => soft_error_count
783  );
784 
785 protocol_error_counter: entity work.error_counter
786  port map (
787  clock => pp_clock,
788  counter_reset => error_counter_reset,
789  system_reset => ipb_rst,
790  error => aurora_chan_stat(11),
791  error_count => protocol_error_count
792  );
793 
794 
795 Frame_error_counter : entity work.error_counter
796  port map (
797  clock => pp_clock,
798  counter_reset => error_counter_reset,
799  system_reset => ipb_rst,
800  error => frame_err,
801  error_count => frame_error_count
802  );
803 
804 --The jfex odd word count error is also considered a "framing error", thus aurora_chan_stat(12) below
805 
806 frame_err <= aurora_chan_stat(10);-- or aurora_chan_stat(12);
807 
808 odd_word_counter : entity work.error_counter
809  port map (
810  clock => pp_clock,
811  counter_reset => error_counter_reset,
812  system_reset => ipb_rst,
813  error => aurora_chan_stat(12),
814  error_count => odd_word_error_count
815  );
816 
817 
818 
819 
820 
821 
822 --CRC error counting: because hdr_crc_tag can last many cycles for a single error, it is necessary to detect a rising edge
823 --process(pp_clock, error_counter_reset, ipb_rst)
824 process(pp_clock, master_reset, ipb_rst)
825  begin
826  -- if (error_counter_reset or ipb_rst) = '1' then -- async (p)reset -> put 'reset in sensitivity list
827  if (master_reset or ipb_rst) = '1' then
828  prev_hdr_crc_tag <= '0';
829  elsif rising_edge(pp_clock) then
830  prev_hdr_crc_tag <= hdr_crc_tag;
831  end if;
832  end process;
833 
834 crc_error <= hdr_crc_tag and not prev_hdr_crc_tag;
835 
836 header_crc_err_counter : entity work.error_counter
837  port map (
838  clock => pp_clock,
839  counter_reset => error_counter_reset,
840  system_reset => ipb_rst,
841  error => crc_error,
842  error_count => header_crc_error_count
843  );
844 
845 
846 
847 --counting trailer crc errors has been removed from the channel due to potential bandwidth issues at 320MHz
848 --and also repeating the same logic for all channels. It is now performed centrally in the processors.
849 --This field will be removed from the XML
850 trailer_crc_error_count <= (others => '0');
851 
852 
853 
854 channel_up <= aurora_chan_stat(0) or chan_disable;
855 
856 chan_reset : channel_init
857  generic map (
858  jfex => jfex
859  )
860  Port map (
861  init_clk => init_clk,
862  chan_reg_reset => chan_reset_trig,
863  bp_reg_reset => bp_reg_reset,
864  master_reset => master_reset,
865  channel_up => channel_up,
866  error_counter_reset => error_counter_reset,
867  aurora_reset_out => aurora_channel_control(30),
868  GT_reset => aurora_channel_control(31),
869  fex_reset => aurora_channel_control(29),
870  self_reset_count => aurora_self_reset_count,
871  chan_up_time => chan_up_time,
872  channel_down_auto_reset_disable => channel_down_auto_reset_disable
873  );
874 
875 
876 probe_self_reset : ila_self_reset
877 PORT MAP (
878  clk => init_clk,
879 
880  probe0(0) => chan_reset_trig,
881  probe1(0) => bp_reg_reset,
882  probe2(0) => master_reset,
883  probe3(0) => channel_up,
884  probe4(0) => error_counter_reset,
885  probe5(0) => aurora_channel_control(29),
886  probe6(0) => aurora_channel_control(30),
887  probe7(0) => aurora_channel_control(31),
888  probe8 => aurora_self_reset_count,
889  probe9 => chan_up_time,
890  probe10(0) => channel_down_auto_reset_disable,
891  probe11(0) => chan_disable,
892  probe12(0) => aurora_chan_stat(0)
893 );
894 
895 
896 
897 chan_len_err_counter : edge_error_counter
898  generic map (
899  cwidth => 4
900  )
901  port map (
902  -- clock => ipb_clk,
903  clock => pp_clock,
904  counter_reset => error_counter_reset,
905  system_reset => ipb_rst,
906  error => pkt_len_violation,
907  error_count => pkt_maxlen_error_count
908  );
909 
910 
911 --ufc_receiver : ufc_rx
912 -- Port map (
913 -- clock => aurora_user_clk,
914 -- reset => ufc_reset,
915 -- axi_ufc_rx_tvalid => s_axi_ufc_rx_tvalid,
916 -- axi_ufc_rx_tlast => s_axi_ufc_rx_tlast,
917 -- axi_ufc_rx_tdata => s_axi_ufc_rx_tdata(15 downto 0),
918 --
919 -- message => ufc_message,
920 -- parity_error => ufc_parity_error,
921 -- channel_Busy => ufc_channel_busy_i
922 --
923 -- );
924 --
925 --ufc_reset <= chan_reset_trig or ipb_rst;
926 
927 
928 UFC_Busy_control_reg : entity work.ipbus_reg_v
929  port map(
930  clk => ipb_clk,
931  reset => ipb_rst,
932  ipbus_in => ipbw(N_SLV_UFC_busy_control),
933  ipbus_out => ipbr(N_SLV_UFC_busy_control),
934  q(0) => ufc_busy_control
935  );
936 
937 --channel_busy <= (ufc_channel_busy and ufc_busy_control(0)) or (tob_fifo_busy and tob_fifo_busy_enable) or (bulk_fifo_busy and bulk_fifo_busy_enable) or (bulk_fifo_force_busy) or (tob_fifo_force_busy);
938 channel_busy <= (ufc_message(0) and ufc_busy_control(0)) or (ufc_message(1) and ufc_busy_control(1)) or (tob_fifo_busy and tob_fifo_busy_enable) or (bulk_fifo_busy and bulk_fifo_busy_enable) or (bulk_fifo_force_busy) or (tob_fifo_force_busy);
939 --channel_xoff <= (tob_fifo_xoff_i and tob_fifo_xoff_enable) or (bulk_fifo_xoff_i and bulk_fifo_xoff_enable);
940 --tob_fifo_xoff <= (tob_fifo_xoff_i and tob_fifo_xoff_enable) or (tob_fifo_force_xoff);
941 aurora_channel_control(6) <= (tob_fifo_xoff_i and tob_fifo_xoff_enable) or (tob_fifo_force_xoff);
942 --bulk_fifo_xoff <= (bulk_fifo_xoff_i and bulk_fifo_xoff_enable) or (bulk_fifo_force_xoff);
943 aurora_channel_control(7) <= (bulk_fifo_xoff_i and bulk_fifo_xoff_enable) or (bulk_fifo_force_xoff);
944 
945 
946 ufc_parity_disable <= ufc_busy_control(8);
947 
948 --FEX_Busy_timer_reset_reg : entity work.ipbus_reg_v
949 -- port map(
950 -- clk => ipb_clk,
951 -- reset => ipb_rst,
952 -- ipbus_in => ipbw(N_SLV_FEX_busy_timer_reset),
953 -- ipbus_out => ipbr(N_SLV_FEX_busy_timer_reset),
954 -- q(0) => ufc_timer_reset
955 -- );
956 
957 FEX_Busy_timer_reset_reg: entity work.ipbus_reg_v
958  port map(
959  clk => ipb_clk,
960  reset => ufc_timer_rst_rst,
961  ipbus_in => ipbw(N_SLV_FEX_busy_timer_reset),
962  ipbus_out => ipbr(N_SLV_FEX_busy_timer_reset),
963  stb(0) => ufc_timer_rst_stb,
964  q(0) => ufc_timer_reset
965  );
966 ufc_timer_rst_rst <= ufc_timer_rst_stb or ipb_rst;
967 
968 
969 
970 
971 Fex_busy_status_reg : entity work.ipbus_syncreg_v
972  generic map (
973  N_CTRL => 0,
974  N_STAT => 1
975  )
976  port map (
977  clk => ipb_clk,
978  rst => ipb_rst,
979  ipb_in => ipbw(N_SLV_Fex_busy_status),
980  ipb_out => ipbr(N_SLV_Fex_busy_status),
981  slv_clk => pp_clock,
982  d(0) => ufc_status(31 downto 0),
983  qmask => (others => (others => '1')),
984  stb => open,
985  rstb => open
986  );
987 
988 ufc_status(2 downto 0) <= ufc_message(2 downto 0);
989 ufc_status(5 downto 3) <= ufc_message(6 downto 4);
990 ufc_status(31 downto 6) <= (others => '0');
991 
992 --ToB Busy timer reg
993 Fex_tob_busy_timer_reg : entity work.ipbus_syncreg_v
994  generic map (
995  N_CTRL => 0,
996  N_STAT => 1
997  )
998  port map (
999  clk => ipb_clk,
1000  rst => ipb_rst,
1001  ipb_in => ipbw(N_SLV_FEX_TOB_BUSY_TIMER),
1002  ipb_out => ipbr(N_SLV_FEX_TOB_BUSY_TIMER),
1003  slv_clk => rt_clk,
1004  d(0) => ufc_timer_0(31 downto 0),
1005  qmask => (others => (others => '1')),
1006  stb => open,
1007  rstb => open
1008  );
1009 
1010 --ToB Busy timer
1011 --process(rt_clk, t_reset(0))
1012 process(pp_clock, t_reset(0))
1013  begin
1014  if t_reset(0) = '1' then -- async (p)reset -> put 'reset in sensitivity list
1015  ufc_timer_0 <= (others => '0');
1016  elsif rising_edge(pp_clock) then
1017  if (ufc_message(0) = '1') then
1018  ufc_timer_0 <= (ufc_timer_0 + 1);
1019  else
1020  ufc_timer_0 <= ufc_timer_0;
1021  end if;
1022  end if;
1023  end process;
1024 
1025  t_reset(0) <= ufc_timer_reset(0) or ipb_rst;
1026 
1027 --RAW Busy timer reg
1028 Fex_raw_busy_timer_reg : entity work.ipbus_syncreg_v
1029  generic map (
1030  N_CTRL => 0,
1031  N_STAT => 1
1032  )
1033  port map (
1034  clk => ipb_clk,
1035  rst => ipb_rst,
1036  ipb_in => ipbw(N_SLV_FEX_RAW_BUSY_TIMER),
1037  ipb_out => ipbr(N_SLV_FEX_RAW_BUSY_TIMER),
1038  slv_clk => rt_clk,
1039  d(0) => ufc_timer_1(31 downto 0),
1040  qmask => (others => (others => '1')),
1041  stb => open,
1042  rstb => open
1043  );
1044 
1045 --RAW Busy timer
1046 --process(rt_clk, t_reset(1))
1047 process(pp_clock, t_reset(1))
1048  begin
1049  if t_reset(1) = '1' then -- async (p)reset -> put 'reset in sensitivity list
1050  ufc_timer_1 <= (others => '0');
1051  elsif rising_edge(pp_clock) then
1052  if (ufc_message(1) = '1') then
1053  ufc_timer_1 <= (ufc_timer_1 + 1);
1054  else
1055  ufc_timer_1 <= ufc_timer_1;
1056  end if;
1057  end if;
1058  end process;
1059 
1060  t_reset(1) <= ufc_timer_reset(1) or ipb_rst;
1061 
1062 --the following timers are removed following the redifinion of Busy into TOB_BUSY and RAW_BUSY
1063 
1064 --Fex_busy_timer_2_reg : entity work.ipbus_syncreg_v
1065 -- generic map (
1066 -- N_CTRL => 0,
1067 -- N_STAT => 1
1068 -- )
1069 -- port map (
1070 -- clk => ipb_clk,
1071 -- rst => ipb_rst,
1072 -- ipb_in => ipbw(N_SLV_Fex_busy_timer_2),
1073 -- ipb_out => ipbr(N_SLV_Fex_busy_timer_2),
1074 -- slv_clk => pp_clock,
1075 -- d(0) => ufc_timer_2(33 downto 2),
1076 -- qmask => (others => (others => '1')),
1077 -- stb => open,
1078 -- rstb => open
1079 -- );
1080 
1081 --process(pp_clock, t_reset(2))
1082 -- begin
1083 -- if t_reset(2) = '1' then -- async (p)reset -> put 'reset in sensitivity list
1084 -- ufc_timer_2 <= (others => '0');
1085 -- elsif rising_edge(pp_clock) then
1086 -- if (ufc_message(2) = '1') then
1087 -- ufc_timer_2 <= (ufc_timer_2 + 4);
1088 -- else
1089 -- ufc_timer_2 <= ufc_timer_2;
1090 -- end if;
1091 -- end if;
1092 -- end process;
1093 
1094 -- t_reset(2) <= ufc_timer_reset(2) or ipb_rst;
1095 
1096 
1097 --Fex_busy_timer_3_reg : entity work.ipbus_syncreg_v
1098 -- generic map (
1099 -- N_CTRL => 0,
1100 -- N_STAT => 1
1101 -- )
1102 -- port map (
1103 -- clk => ipb_clk,
1104 -- rst => ipb_rst,
1105 -- ipb_in => ipbw(N_SLV_Fex_busy_timer_3),
1106 -- ipb_out => ipbr(N_SLV_Fex_busy_timer_3),
1107 -- slv_clk => pp_clock,
1108 -- d(0) => ufc_timer_3(33 downto 2),
1109 -- qmask => (others => (others => '1')),
1110 -- stb => open,
1111 -- rstb => open
1112 -- );
1113 --
1114 --process(pp_clock, t_reset(3))
1115 -- begin
1116 -- if t_reset(3) = '1' then -- async (p)reset -> put 'reset in sensitivity list
1117 -- ufc_timer_3 <= (others => '0');
1118 -- elsif rising_edge(pp_clock) then
1119 -- if (ufc_message(4) = '1') then --!ufc_message(4) is counted by timer 3 becasue ufc_message(3) is parity
1120 -- ufc_timer_3 <= (ufc_timer_3 + 4);
1121 -- else
1122 -- ufc_timer_3 <= ufc_timer_3;
1123 -- end if;
1124 -- end if;
1125 -- end process;
1126 
1127 -- t_reset(3) <= ufc_timer_reset(3) or ipb_rst;
1128 
1129 
1130 --Fex_busy_timer_4_reg : entity work.ipbus_syncreg_v
1131 -- generic map (
1132 -- N_CTRL => 0,
1133 -- N_STAT => 1
1134 -- )
1135 -- port map (
1136 -- clk => ipb_clk,
1137 -- rst => ipb_rst,
1138 -- ipb_in => ipbw(N_SLV_Fex_busy_timer_4),
1139 -- ipb_out => ipbr(N_SLV_Fex_busy_timer_4),
1140 -- slv_clk => pp_clock,
1141 -- d(0) => ufc_timer_4(33 downto 2),
1142 -- qmask => (others => (others => '1')),
1143 -- stb => open,
1144 -- rstb => open
1145 -- );
1146 
1147 --process(pp_clock, t_reset(4))
1148 -- begin
1149 -- if t_reset(4) = '1' then -- async (p)reset -> put 'reset in sensitivity list
1150 -- ufc_timer_4 <= (others => '0');
1151 -- elsif rising_edge(pp_clock) then
1152 -- if (ufc_message(5) = '1') then
1153 -- ufc_timer_4 <= (ufc_timer_4 + 4);
1154 -- else
1155 -- ufc_timer_4 <= ufc_timer_4;
1156 -- end if;
1157 -- end if;
1158 -- end process;
1159 
1160 -- t_reset(4) <= ufc_timer_reset(4) or ipb_rst;
1161 
1162 
1163 --Fex_busy_timer_5_reg : entity work.ipbus_syncreg_v
1164 -- generic map (
1165 -- N_CTRL => 0,
1166 -- N_STAT => 1
1167 -- )
1168 -- port map (
1169 -- clk => ipb_clk,
1170 -- rst => ipb_rst,
1171 -- ipb_in => ipbw(N_SLV_Fex_busy_timer_5),
1172 -- ipb_out => ipbr(N_SLV_Fex_busy_timer_5),
1173 -- slv_clk => pp_clock,
1174 -- d(0) => ufc_timer_5(33 downto 2),
1175 -- qmask => (others => (others => '1')),
1176 -- stb => open,
1177 -- rstb => open
1178 -- );
1179 
1180 --process(pp_clock, t_reset(5))
1181 -- begin
1182 -- if t_reset(5) = '1' then -- async (p)reset -> put 'reset in sensitivity list
1183 -- ufc_timer_5 <= (others => '0');
1184 -- elsif rising_edge(pp_clock) then
1185 -- if (ufc_message(6) = '1') then
1186 -- ufc_timer_5 <= (ufc_timer_5 + 4);
1187 -- else
1188 -- ufc_timer_5 <= ufc_timer_5;
1189 -- end if;
1190 -- end if;
1191 -- end process;
1192 
1193 -- t_reset(5) <= ufc_timer_reset(5) or ipb_rst;
1194 
1195 
1196 
1197 --UFC parity error count register
1198 UFC_parity_error_count_reg : entity work.ipbus_syncreg_v
1199  generic map (
1200  N_CTRL => 0,
1201  N_STAT => 1
1202  )
1203  port map (
1204  clk => ipb_clk,
1205  rst => ipb_rst,
1206  ipb_in => ipbw(N_SLV_UFC_PARITY_ERROR_COUNT),
1207  ipb_out => ipbr(N_SLV_UFC_PARITY_ERROR_COUNT),
1208  slv_clk => aurora_user_clk,
1209  d(0) => ufc_parity_count,
1210  qmask => (others => (others => '1')),
1211  stb => open,
1212  rstb => open
1213  );
1214 
1215 t_reset(8) <= ufc_timer_reset(8) or ipb_rst;
1216 
1217 --UFC parity error counter
1218 --process(aurora_user_clk, t_reset(8))
1219 process(pp_clock, t_reset(8))
1220  begin
1221  if t_reset(8) = '1' then -- async (p)reset -> put 'reset in sensitivity list
1222  ufc_parity_count <= (others => '0');
1223  elsif rising_edge(pp_clock) then
1224  if (ufc_parity_error = '1') and (ufc_parity_count /= 0x"FFFF") then
1225  ufc_parity_count <= (ufc_parity_count + 1);
1226  else
1227  ufc_parity_count <= ufc_parity_count;
1228  end if;
1229  end if;
1230  end process;
1231 
1232 Aurora_self_reset_count_reg: entity work.ipbus_syncreg_v
1233  generic map (
1234  N_CTRL => 0,
1235  N_STAT => 1
1236  )
1237  port map (
1238  clk => ipb_clk,
1239  rst => ipb_rst,
1240  ipb_in => ipbw(N_SLV_AURORA_AUTO_RESET_COUNT),
1241  ipb_out => ipbr(N_SLV_AURORA_AUTO_RESET_COUNT),
1242  slv_clk => init_clk,
1243  d(0) => aurora_self_reset_count,
1244  qmask => (others => (others => '1')),
1245  stb => open,
1246  rstb => open
1247  );
1248 
1249 Aurora_channel_up_timer_reg: entity work.ipbus_syncreg_v
1250  generic map (
1251  N_CTRL => 0,
1252  N_STAT => 1
1253  )
1254  port map (
1255  clk => ipb_clk,
1256  rst => ipb_rst,
1257  ipb_in => ipbw(N_SLV_AURORA_CHAN_UP_TIME),
1258  ipb_out => ipbr(N_SLV_AURORA_CHAN_UP_TIME),
1259  slv_clk => init_clk,
1260  d(0) => chan_up_time,
1261  qmask => (others => (others => '1')),
1262  stb => open,
1263  rstb => open
1264  );
1265 
1266 
1267  TOB_rcv_timer_reg: entity work.ipbus_syncreg_v
1268  generic map (
1269  N_CTRL => 0,
1270  N_STAT => 1
1271  )
1272  port map (
1273  clk => ipb_clk,
1274  rst => ipb_rst,
1275  ipb_in => ipbw(N_SLV_TOB_RX_TIMER),
1276  ipb_out => ipbr(N_SLV_TOB_RX_TIMER),
1277  slv_clk => pp_clock,
1278  d(0) => tob_rx_time_max & tob_rx_time ,
1279  qmask => (others => (others => '1')),
1280  stb => open,
1281  rstb => open
1282  );
1283 
1284 tob_rcv_timer : tob_rx_timer
1285  Port map (
1286  pp_clock => pp_clock,
1287  L1A => L1A,
1288  s_tvalid => s_tvalid,
1289  reset => tob_fifo_reset(4),
1290  tob_rx_time => tob_rx_time,
1291  tob_rx_time_max => tob_rx_time_max
1292  );
1293 
1294  Tob_l1id_repeat_reg : entity work.ipbus_syncreg_v
1295  generic map (
1296  N_CTRL => 0,
1297  N_STAT => 1
1298  )
1299  port map (
1300  clk => ipb_clk,
1301  rst => ipb_rst,
1302  ipb_in => ipbw(N_SLV_Tob_repeat_l1ID_counter),
1303  ipb_out => ipbr(N_SLV_Tob_repeat_l1ID_counter),
1304  slv_clk => pp_clock,
1305  d(0) => repeat_l1id_counter,
1306  qmask => (others => (others => '1')),
1307  stb => open,
1308  rstb => open
1309  );
1310 
1311 Tob_packets_read_reg : entity work.ipbus_syncreg_v
1312  generic map (
1313  N_CTRL => 0,
1314  N_STAT => 1
1315  )
1316  port map (
1317  clk => ipb_clk,
1318  rst => ipb_rst,
1319  ipb_in => ipbw(N_SLV_Tob_packets_read),
1320  ipb_out => ipbr(N_SLV_Tob_packets_read),
1321  slv_clk => pp_clock,
1322  d(0) => packets_read_counter,
1323  qmask => (others => (others => '1')),
1324  stb => open,
1325  rstb => open
1326  );
1327 
1328 
1329 end RTL;
channel_init
Definition: channel_init.vhd:34
edge_error_counter
Definition: edge_error_counter.vhd:38
error_counter
Definition: error_counter.vhd:37
fex_chan_regs.RTL
Definition: fex_chan_regs.vhd:133
fex_chan_regs
Definition: fex_chan_regs.vhd:46
pulse_stretch
Definition: pulse_stretch.vhd:35
threshold_counter
Definition: threshold_counter.vhd:29
tob_rx_timer
Definition: tob_rx_timer.vhd:35
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