channel_init.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 17.01.2019 18:20:31
-- Design Name: 
-- Module Name: channel_init - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity channel_init is
   generic (
       jfex   : integer :=   0       
   );   
    Port ( 
           init_clk             : in STD_LOGIC; 
           chan_reg_reset       : in STD_LOGIC;
           bp_reg_reset         : in STD_LOGIC;
           master_reset       : in STD_LOGIC;
           channel_up           : in STD_LOGIC;  
           error_counter_reset  : in STD_LOGIC;         
           aurora_reset_out     : out STD_LOGIC;
           GT_reset             : out STD_LOGIC;
           fex_reset            : out STD_LOGIC;
           self_reset_count     : out std_logic_vector(31 downto 0);
           chan_up_time         : out std_logic_vector(31 downto 0);
           channel_down_auto_reset_disable : in std_logic 
           );
           
 
end channel_init;
 
architecture RTL of channel_init is
 
component aurora_reset
--  Port ( );
    Port ( init_clk : in STD_LOGIC;
       BTN0 : in STD_LOGIC;
       rst_sw : in STD_LOGIC;
       tx_reset : out STD_LOGIC;          
       tx_GTReset : out STD_LOGIC := '0';
       rx_reset : out STD_LOGIC;
       rx_GTReset : out STD_LOGIC := '0');
end component;
 
component self_reset 
  generic
    (            
            GAP_WIDTH   : integer :=   17;
                   -- width of gap counter ex; 5 makes gap of 32 cycles
             jfex      : integer :=   0          
    );  
    Port ( 
            clock : in STD_LOGIC;
            channel_up :  in STD_LOGIC;
            reset_in   : in STD_LOGIC;       --must be the OR of other reset sources 
            aurora_reset : in STD_LOGIC;
            error_counter_reset: in STD_LOGIC;
            channel_down_auto_reset_disable : in STD_LOGIC;
            reset_out   : out std_logic;
            reset_count : out std_logic_vector(31 downto 0);
            chan_up_time : out std_logic_vector(31 downto 0)         
            );
end component;
 
component pulse_stretch 
    generic (
 COUNTER_WIDTH  : integer :=   5       
   );    
    Port ( 
          clock : in STD_LOGIC;
          reset :  in STD_LOGIC;
          pulse_in : in STD_LOGIC;
          pulse_out : out STD_LOGIC
                   
          );
end component;
 
 
signal start_seq : STD_LOGIC;
signal chan_good  : STD_LOGIC := '0';
signal rx_reset   : STD_LOGIC;
signal chan_down  : STD_LOGIC := '0';
signal reset_in   : std_logic; 
signal reg_pulse  : std_logic;
signal stretch_pulse : std_logic;
 
begin
 
reg_pulse <= chan_reg_reset or bp_reg_reset; 
 
stretcher : pulse_stretch
  generic map (
                COUNTER_WIDTH => 5       
            )    
  port map (
               clock => init_clk,
               reset => master_reset,
               pulse_in => reg_pulse,
               pulse_out => stretch_pulse
            );        
 
 
 
--reset_in <= master_reset or chan_reg_reset or bp_reg_reset; 
reset_in <= master_reset or stretch_pulse; 
 
reset_timer  : aurora_reset
  PORT MAP (
  init_clk => init_clk,
  BTN0 => start_seq,   --'0',
  rst_sw => '0',       --start_seq,
  tx_reset => open,
  tx_GTReset => open,
  rx_reset => rx_reset,
  rx_GTReset => GT_reset
  );
  
 
self_reset_inst : self_reset 
  Generic Map (    
            GAP_WIDTH   => 20,      -- width of gap counter ex; 5 makes gap of 32 cycles  
            jfex        => jfex 
    )   
  PORT MAP (
  clock => init_clk, 
  channel_up => channel_up,
  reset_in    =>  reset_in,
  aurora_reset => rx_reset,
  error_counter_reset => error_counter_reset,
  channel_down_auto_reset_disable => channel_down_auto_reset_disable,
  reset_out   => start_seq, 
  reset_count => self_reset_count,
  chan_up_time => chan_up_time
  );
  
  
 aurora_reset_out <= rx_reset;
 fex_reset <= start_seq;
 
 
 
 
  
--  start_seq <= chan_down or reg_reset;
  
process (init_clk) begin
        if rising_edge (init_clk) then  
               if channel_up = '1' and rx_reset = '0' then 
                    chan_good <= '1';
--               elsif chan_good = '1' and channel_up = '0' then 
               elsif rx_reset = '0' and channel_up = '0' then 
                    chan_down <= '1';
                    chan_good <= '0';
               elsif chan_down = '1' then 
                    chan_down <= '0';
               end if;
         end if; 
 end process; 
                     
  
  
 
end RTL;