RTL Architecture Reference

Processes
PROCESS_166	( pp_clock , master_reset , ipb_rst )
PROCESS_167	( pp_clock , t_reset( 0 ) )
PROCESS_168	( pp_clock , t_reset( 1 ) )
PROCESS_169	( pp_clock , t_reset( 8 ) )

Components
pulse_stretch	<Entity pulse_stretch>
channel_init	<Entity channel_init>
ila_self_reset
edge_error_counter	<Entity edge_error_counter>
tob_rx_timer	<Entity tob_rx_timer>

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
tob_fifo_control	std_logic_vector ( 31 downto 0 )
Tob_fifo_status	std_logic_vector ( 31 downto 0 )
Tob_fifo_fill_level	std_logic_vector ( 31 downto 0 )
Tob_fifo_busy_Count	std_logic_vector ( 31 downto 0 )
Tob_fifo_xoff_count	std_logic_vector ( 31 downto 0 )
bulk_fifo_control	std_logic_vector ( 31 downto 0 )
bulk_fifo_status	std_logic_vector ( 31 downto 0 )
bulk_fifo_fill_level	std_logic_vector ( 31 downto 0 )
bulk_fifo_busy_Count	std_logic_vector ( 31 downto 0 )
bulk_fifo_xoff_count	std_logic_vector ( 31 downto 0 )
Aurora_channel_status	std_logic_vector ( 31 downto 0 )
data_integrity_status	std_logic_vector ( 31 downto 0 )
hard_error_count	std_logic_vector ( 3 downto 0 )
soft_error_count	std_logic_vector ( 3 downto 0 )
frame_error_count	std_logic_vector ( 3 downto 0 )
protocol_error_count	std_logic_vector ( 3 downto 0 )
header_crc_error_count	std_logic_vector ( 3 downto 0 )
trailer_crc_error_count	std_logic_vector ( 3 downto 0 )
odd_word_error_count	std_logic_vector ( 3 downto 0 )
aurora_channel_control_i	std_logic_vector ( 31 downto 0 )
error_counter_reset	std_logic
tob_counter_reset	std_logic
bulk_busy_counter_reset	std_logic
bulk_xoff_counter_reset	std_logic
tfifo_xoff_tcount	std_logic_vector ( 31 downto 0 )
channel_control_reset	std_logic
channel_control_stb	std_logic
channel_reset_pulse	std_logic
tob_fifo_rst_rst	std_logic
tob_fifo_rst_stb	std_logic
tob_fifo_reset	std_logic_vector ( 31 downto 0 )
bulk_fifo_rst_rst	std_logic
bulk_fifo_rst_stb	std_logic
bulk_fifo_reset	std_logic_vector ( 31 downto 0 )
aurora_reset_disable_i	std_logic_vector ( 31 downto 0 )
channel_down_auto_reset_disable	std_logic
pkt_len_violation_auto_reset_disable	std_logic
chan_reset_trig	std_logic
channel_up	std_logic
crc_error	std_logic
prev_hdr_crc_tag	std_logic
frame_err	std_logic
tob_watermark_reset	std_logic
tob_watermark	std_logic_vector ( 15 downto 0 )
bulk_watermark_reset	std_logic
bulk_watermark	std_logic_vector ( 15 downto 0 )
pkt_maxlen_error_count	std_logic_vector ( 3 downto 0 )
ufc_channel_Busy_i	std_logic
ufc_reset	std_logic
ufc_timer_0	std_logic_vector ( 33 downto 0 )
ufc_timer_1	std_logic_vector ( 33 downto 0 )
ufc_timer_2	std_logic_vector ( 33 downto 0 )
ufc_timer_3	std_logic_vector ( 33 downto 0 )
ufc_timer_4	std_logic_vector ( 33 downto 0 )
ufc_timer_5	std_logic_vector ( 33 downto 0 )
ufc_timer_reset	std_logic_vector ( 31 downto 0 )
t_reset	std_logic_vector ( 31 downto 0 )
ufc_status	std_logic_vector ( 31 downto 0 )
ufc_busy_control	std_logic_vector ( 31 downto 0 )
ufc_parity_count	std_logic_vector ( 31 downto 0 )
ufc_timer_rst_rst	std_logic
ufc_timer_rst_stb	std_logic
tob_fifo_busy	std_logic
tob_fifo_xoff_i	std_logic
bulk_fifo_busy	std_logic
bulk_fifo_xoff_i	std_logic
tob_fifo_busy_enable	std_logic
tob_fifo_xoff_enable	std_logic
tob_fifo_force_busy	std_logic
bulk_fifo_busy_enable	std_logic
bulk_fifo_xoff_enable	std_logic
bulk_fifo_force_busy	std_logic
tob_fifo_force_xoff	std_logic
bulk_fifo_force_xoff	std_logic
aurora_self_reset_count	std_logic_vector ( 31 downto 0 )
chan_up_time	std_logic_vector ( 31 downto 0 )
tob_rx_time	std_logic_vector ( 15 downto 0 )
tob_rx_time_max	std_logic_vector ( 15 downto 0 )

Instantiations
fabric	ipbus_fabric_sel
tob_fifo_control_reg	ipbus_reg_v
tob_fifo_reset_reg	ipbus_reg_v
tob_fifo_status_reg	ipbus_syncreg_v
tob_fifo_fill_level_reg	ipbus_syncreg_v
tob_fifo_watermark	watermark <Entity watermark>
tob_fifo_busy_count_reg	ipbus_syncreg_v
tob_fifo_busy_counter	threshold_counter <Entity threshold_counter>
tob_fifo_xoff_count_reg	ipbus_syncreg_v
tob_fifo_xoff_counter	threshold_counter <Entity threshold_counter>
bulk_fifo_control_reg	ipbus_reg_v
bulk_fifo_reset_reg	ipbus_reg_v
bulk_fifo_status_reg	ipbus_syncreg_v
bulk_fifo_fill_level_reg	ipbus_syncreg_v
bulk_fifo_watermark	watermark <Entity watermark>
bulk_fifo_busy_count_reg	ipbus_syncreg_v
bulk_fifo_busy_counter	threshold_counter <Entity threshold_counter>
bulk_fifo_xoff_count_reg	ipbus_syncreg_v
bulk_fifo_xoff_counter	threshold_counter <Entity threshold_counter>
aurora_channel_control_reg	ipbus_reg_v
aurora_reset_pulse	pulse_stretch <Entity pulse_stretch>
aurora_autoreset_disable	ipbus_reg_v
aurora_channel_status_reg	ipbus_syncreg_v
data_integrity_status_reg	ipbus_syncreg_v
hard_error_counter	error_counter <Entity error_counter>
soft_error_counter	error_counter <Entity error_counter>
protocol_error_counter	error_counter <Entity error_counter>
frame_error_counter	error_counter <Entity error_counter>
odd_word_counter	error_counter <Entity error_counter>
header_crc_err_counter	error_counter <Entity error_counter>
chan_reset	channel_init <Entity channel_init>
probe_self_reset	ila_self_reset
chan_len_err_counter	edge_error_counter <Entity edge_error_counter>
ufc_busy_control_reg	ipbus_reg_v
fex_busy_timer_reset_reg	ipbus_reg_v
fex_busy_status_reg	ipbus_syncreg_v
fex_tob_busy_timer_reg	ipbus_syncreg_v
fex_raw_busy_timer_reg	ipbus_syncreg_v
ufc_parity_error_count_reg	ipbus_syncreg_v
aurora_self_reset_count_reg	ipbus_syncreg_v
aurora_channel_up_timer_reg	ipbus_syncreg_v
tob_rcv_timer_reg	ipbus_syncreg_v
tob_rcv_timer	tob_rx_timer <Entity tob_rx_timer>
tob_l1id_repeat_reg	ipbus_syncreg_v
tob_packets_read_reg	ipbus_syncreg_v

Detailed Description

Definition at line 133 of file fex_chan_regs.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/fex_chan_regs.vhd