ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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channel_fifo.vhd
1 ----------------------------------------------------------------------------------
2 -- Company: University of Cambridge
3 -- Engineer: Ed Flaherty
4 --
5 -- Create Date: 14.07.2018 16:51:58
6 -- Design Name:
7 -- Module Name: channel_fifo - RTL
8 -- Project Name: ROD
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description: This is the input structure for the packet processor. It connects to one
12 -- 64-bit Aurora receiver channel. One of these should be instanced for each Fex data channel (12 in the case of eFex)
13 -- It provides clock crossing fifos to move from the Aurora clock to the
14 -- 160MHz packet processor clock. There are separate fifos for TOBs and for bulk input "calo" data
15 -- It streams a single packet out of the fifo to the event builder when the POLL input
16 -- is asserted for one cycle
17 --
18 -- This version is currently specific to the eFex 64-bit data input. In the jFex version, an additional 64-bit register will be
19 -- added to assemble the input into 64-bit words before being placed into the fifo.
20 --
21 -- TKEEP signals have been removed since the last word of a packet is always the trailer and is
22 -- a full 64-bit word.
23 --
24 -- word counting and associated error checking has been removed from here and moved to the event builder
25 
26 --
27 -- Dependencies:
28 --
29 -- Revision:
30 -- Revision 0.01 - File Created
31 -- Additional Comments:
32 --
33 ----------------------------------------------------------------------------------
34 
35 
36 library IEEE;
37 use IEEE.STD_LOGIC_1164.ALL;
38 use ieee.std_logic_unsigned.all;
39 -- Uncomment the following library declaration if using
40 -- arithmetic functions with Signed or Unsigned values
41 use IEEE.NUMERIC_STD.ALL;
42 use work.ipbus.all;
43 
44 -- Uncomment the following library declaration if instantiating
45 -- any Xilinx leaf cells in this code.
46 --library UNISIM;
47 --use UNISIM.VComponents.all;
48 
62 
79 
80 
93 
94 entity channel_fifo is
95  generic (
96 -- packet header definition
97 
98 
99  channel_num : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
100  lmem : STD_LOGIC_VECTOR (3 downto 0) := "0000";
101  max_packet_length : STD_LOGIC_VECTOR (15 downto 0) := x"02FF";
102 
103  sim : integer := 0;
104  debug : integer := 1;
105  axi_fifo : integer := 0;
106  jfex : integer := 0;
107  bp_width : integer := 64;
108  fifo_instr : integer := 0;
109 
110 
111 -- source_lsb : integer := 16;
112 -- source_msb : integer := 19;
113  length_lsb : integer := 20;
114  length_msb : integer := 31
115 -- dest_addr_lsb : integer := 32;
116 -- dest_addr_msb : integer := 39;
117 -- bcn_lsb : integer := 40;
118 -- bcn_msb : integer := 51;
119 -- type_lsb : integer := 52;
120 -- type_msb : integer := 55;
121 -- version_lsb : integer := 56;
122 -- version_msb : integer := 59;
123 -- L1ID_lsb : integer := 60;
124 -- L1ID_msb : integer := 83
125  );
126 
127 Port (
128 
129  ipb_clk : in std_logic;
130  ipb_rst : in std_logic;
131  ipb_in : in ipb_wbus;
132  ipb_out : out ipb_rbus;
133 
134 ----inputs from Aurora ---------------------------------
135  aurora_chan_stat : in STD_LOGIC_VECTOR (31 downto 0);
136 
137 
138  tob_fifo_busy_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
139  bulk_fifo_busy_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
140  tob_fifo_xoff_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
141  bulk_fifo_xoff_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
142 
143  time_count : in STD_LOGIC_VECTOR (31 downto 0); --synchronous to the pp_clock
144  aurora_channel_control : out STD_LOGIC_VECTOR (31 downto 0); --synchronous to ipb_clk
145  backplane_control : in STD_LOGIC_VECTOR (31 downto 0);
146  chan_disable : in std_logic;
147  init_clk : in std_logic;
148  bp_reg_reset : in std_logic;
149  master_reset : in std_logic;
150  wdog_fifo_reset : in STD_LOGIC;
151 
152 --need to merge fifo resets in with channel control
153  RESET : in std_logic;
154  clk_160 : in std_logic;
155  rt_clk : in std_logic;
156  aurora_user_clk : in std_logic;
157  pp_clock : in std_logic;
158  s_axis_tvalid : in std_logic;
159  s_axis_tlast : in std_logic;
160  tob_s_tready : out std_logic;
161  s_axis_tdata : in std_logic_vector((bp_width-1) downto 0);
162  -- s_axis_tkeep : in std_logic_vector(((bp_width/8) -1) downto 0);
163 
164 --tob output axi bus --------------------------------------
165  poll_chan : in std_logic;
166 
167  tob_m_tvalid : out std_logic;
168  tob_m_tlast : out std_logic;
169  tob_m_tready : in std_logic;
170  tob_m_tdata : out std_logic_vector((bp_width-1) downto 0);
171 -- m_header_marker : out std_logic;
172 -- m_tail_marker : out std_logic;
173  tob_header_marker : out std_logic;
174  tob_tail_marker : out std_logic;
175  hdr_crc_tag : out std_logic;
176  comb_error_tag : out std_logic;
177 
178  --calo output axi bus --------------------------------------
179  calo_poll_chan : in std_logic;
180  calo_m_tvalid : out std_logic;
181  calo_m_fifo_tlast : out std_logic;
182  calo_m_axis_tready : in std_logic;
183  calo_s_axis_tready : out std_logic;
184 
185  calo_m_axis_tdata : out std_logic_vector((bp_width-1) downto 0);
186  calo_header_marker : out std_logic;
187  calo_tail_marker : out std_logic;
188 
189  --ufc message axi bus --------------------------------------
190  s_axi_ufc_rx_tdata : in std_logic_vector(63 downto 0);
191  s_axi_ufc_rx_tvalid : in std_logic;
192  s_axi_ufc_rx_tlast : in std_logic;
193 
194  channel_busy : out std_logic;
195  timeout_err : in std_logic;
196  L1A : in std_logic
197  );
198 
199 
200 end channel_fifo;
201 
202 architecture RTL of channel_fifo is
203 
204 component aurora_pipe
205  generic (
206  channel_num : STD_LOGIC_VECTOR (11 downto 0) := channel_num;
207  lmem : STD_LOGIC_VECTOR (3 downto 0) := lmem;
208  max_packet_length : STD_LOGIC_VECTOR (15 downto 0) := max_packet_length
209  );
210  Port ( pp_clock : in STD_LOGIC;
211  aurora_user_clk : in STD_LOGIC;
212  reset : in STD_LOGIC;
213  aurora_chan_stat : in STD_LOGIC_VECTOR (31 downto 0);
214  s_axis_tvalid : in STD_LOGIC;
215  s_axis_tlast : in STD_LOGIC;
216  s_axis_tdata : in STD_LOGIC_VECTOR (63 downto 0);
217  m_axis_tvalid : out STD_LOGIC;
218  m_axis_tlast : out STD_LOGIC;
219  m_axis_tdata : out STD_LOGIC_VECTOR (63 downto 0);
220  m_first_cyc : out STD_LOGIC;
221  crc_error : out STD_LOGIC;
222  m_tval_tob : out STD_LOGIC;
223  m_tval_calo : out STD_LOGIC;
224  pkt_len_violation : out STD_LOGIC;
225  comb_error : in STD_LOGIC;
226  m_comb_error : out std_logic
227  );
228 end component;
229 
230 
231 
232 
233 
234 COMPONENT clock_cross_fifo
235  PORT (
236  m_aclk : IN STD_LOGIC;
237  s_aclk : IN STD_LOGIC;
238  s_aresetn : IN STD_LOGIC;
239  s_axis_tvalid : IN STD_LOGIC;
240  s_axis_tready : OUT STD_LOGIC;
241  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
242  s_axis_tlast : IN STD_LOGIC;
243  s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
244  m_axis_tvalid : OUT STD_LOGIC;
245  m_axis_tready : IN STD_LOGIC;
246  m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
247  m_axis_tlast : OUT STD_LOGIC;
248  m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
249  axis_wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
250  axis_rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
251 -- axis_prog_full : OUT STD_LOGIC
252  );
253 END COMPONENT;
254 
255 COMPONENT dual_input_fifo_4K
256  PORT (
257  m_aclk : IN STD_LOGIC;
258  s_aclk : IN STD_LOGIC;
259  s_aresetn : IN STD_LOGIC;
260  s_axis_tvalid : IN STD_LOGIC;
261  s_axis_tready : OUT STD_LOGIC;
262  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
263  s_axis_tlast : IN STD_LOGIC;
264  s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
265  m_axis_tvalid : OUT STD_LOGIC;
266  m_axis_tready : IN STD_LOGIC;
267  m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
268  m_axis_tlast : OUT STD_LOGIC;
269  m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
270  axis_wr_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
271  axis_rd_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
272 -- axis_prog_full : OUT STD_LOGIC
273  );
274 END COMPONENT;
275 
276 COMPONENT jfex_test_fifo_2 --jfex_test_input_fifo
277  Port (
278  m_aclk : IN STD_LOGIC;
279  s_aclk : IN STD_LOGIC;
280  s_aresetn : IN STD_LOGIC;
281  s_axis_tvalid : IN STD_LOGIC;
282  s_axis_tready : OUT STD_LOGIC;
283  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
284  s_axis_tlast : IN STD_LOGIC;
285  s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
286  m_axis_tvalid : OUT STD_LOGIC;
287  m_axis_tready : IN STD_LOGIC;
288  m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
289  m_axis_tlast : OUT STD_LOGIC;
290  m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
291  axis_wr_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
292  axis_rd_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
293  timeout_err : in std_logic
294  );
295  END COMPONENT;
296 
297 
298 COMPONENT axis_input_fifo
299  PORT (
300  s_axis_aresetn : IN STD_LOGIC;
301  s_axis_aclk : IN STD_LOGIC;
302  s_axis_tvalid : IN STD_LOGIC;
303  s_axis_tready : OUT STD_LOGIC;
304  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
305  s_axis_tlast : IN STD_LOGIC;
306  s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
307  m_axis_aclk : IN STD_LOGIC;
308  m_axis_tvalid : OUT STD_LOGIC;
309  m_axis_tready : IN STD_LOGIC;
310  m_axis_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
311  m_axis_tlast : OUT STD_LOGIC;
312  m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
313  axis_wr_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
314  axis_rd_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
315  );
316 END COMPONENT;
317 
318 
319 
320 --component frag_len_fifo
321 -- Port ( clk : in STD_LOGIC;
322 -- srst : in STD_LOGIC;
323 -- din : in STD_LOGIC_VECTOR (11 downto 0);
324 -- wr_en : in STD_LOGIC;
325 -- rd_en : in STD_LOGIC;
326 -- full : out STD_LOGIC;
327 -- empty : out STD_LOGIC;
328 -- dout : out STD_LOGIC_VECTOR (11 downto 0)
329 -- );
330 --end component;
331 
332 COMPONENT aurora_fifo_in_ila
333 
334 PORT (
335  clk : IN STD_LOGIC;
336  probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
337  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
338  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
339  probe3 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
340  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
341  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
342  probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
343  probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
344  probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
345  probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
346  probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
347  probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
348  probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
349  probe13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
350  probe14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
351  probe15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
352  probe16 : IN STD_LOGIC_VECTOR(2 DOWNTO 0)
353 );
354 END COMPONENT ;
355 COMPONENT aurora_fifo_out_ila
356 
357 PORT (
358  clk : IN STD_LOGIC;
359 
360  probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
361  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
362  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
363  probe3 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
364  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
365  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
366  probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
367  probe7 : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
368  probe8 : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
369  probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
370 );
371 END COMPONENT ;
372 
373 COMPONENT data_fifo_vio
374  PORT (
375  clk : IN STD_LOGIC;
376  probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
377  probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
378  );
379 END COMPONENT;
380 
381 
382 component fex_chan_regs
383  generic (
384  jfex : integer := 0
385  );
386  port(
387  ipb_clk: in std_logic;
388  ipb_rst: in std_logic;
389  ipb_in: in ipb_wbus;
390  ipb_out: out ipb_rbus;
391 
392  pp_clock : in std_logic;
393  clk_160 : in std_logic;
394  rt_clk : in std_logic;
395 
396  aurora_user_clk : in std_logic;
397  aurora_chan_stat : in STD_LOGIC_VECTOR (31 downto 0);
398  tob_fifo_level: in STD_LOGIC_VECTOR (15 downto 0);
399  bulk_fifo_level: in STD_LOGIC_VECTOR (15 downto 0);
400  time_count : in STD_LOGIC_VECTOR (31 downto 0); --synchronous to the pp_clock
401 
402 
403  tob_fifo_busy_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
404 
405  bulk_fifo_busy_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
406  tob_fifo_xoff_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
407  bulk_fifo_xoff_threshold : in STD_LOGIC_VECTOR (15 downto 0); --synchronous to ipb_clk
408 
409  hdr_crc_tag : in std_logic;
410 
411  aurora_channel_control : out STD_LOGIC_VECTOR (31 downto 0); --synchronous to ipb_clk
412  chan_disable : in std_logic;
413  init_clk : in std_logic;
414  bp_reg_reset : in std_logic;
415  master_reset : in std_logic;
416 
417  pkt_len_violation : in STD_LOGIC;
418 
419  --ufc message axi bus --------------------------------------
420 -- s_axi_ufc_rx_tdata : in std_logic_vector(63 downto 0);
421 -- s_axi_ufc_rx_tvalid : in std_logic;
422 -- s_axi_ufc_rx_tlast : in std_logic
423  ufc_message : in STD_LOGIC_Vector(7 downto 0);
424  ufc_parity_error : in STD_LOGIC;
425  ufc_channel_Busy : in STD_LOgic;
426  ufc_parity_disable : out std_logic;
427  channel_busy : out std_logic;
428 
429  L1A : in std_logic;
430  s_tvalid : in std_logic;
431  repeat_l1id_counter : in STD_LOGIC_vector(31 downto 0);
432  repeat_l1id_counter_reset : out STD_LOGIC;
433  packets_read_counter : in STD_LOGIC_vector(31 downto 0);
434  packets_read_counter_reset: out STD_LOGIC
435 
436 
437 -- cfifo_xoff_ena : out std_logic;
438 -- tfifo_xoff_ena : out std_logic;
439 
440 -- stat_reg_out : out std_logic_vector (31 downto 0)
441 -- ctrl_out : out std_logic_vector (31 downto 0)
442 
443  );
444 end component;
445 
446 component ufc_rx
447  Port ( clock : in STD_LOGIC;
448  reset : in STD_LOGIC;
449  axi_ufc_rx_tvalid : in STD_LOGIC;
450  axi_ufc_rx_tlast : in STD_LOGIC;
451  axi_ufc_rx_tdata : in STD_LOGIC_Vector(15 downto 0);
452 
453  ufc_message : out STD_LOGIC_Vector(7 downto 0);
454  ufc_parity_error : out STD_LOGIC;
455  ufc_parity_disable : out std_logic;
456  ufc_channel_busy : out STD_LOGIC
457 
458  );
459 end component;
460 
461 component pulse_stretch is
462  generic (
463  COUNTER_WIDTH : integer := 5
464  );
465  Port (
466  clock : in STD_LOGIC;
467  reset : in STD_LOGIC;
468  pulse_in : in STD_LOGIC;
469  pulse_out : out STD_LOGIC
470 
471  );
472 end component;
473 
474 
475 signal m_axis_tready : STD_LOGIC;
476 signal tob_m_axis_tdata : STD_LOGIC_VECTOR ((bp_width-1) downto 0);
477 
478 signal axis_data_count : STD_LOGIC_VECTOR (31 downto 0);
479 signal axis_wr_data_count : STD_LOGIC_VECTOR (10 downto 0);
480 signal axis_rd_data_count : STD_LOGIC_VECTOR (10 downto 0);
481 signal s_axis_aresetn : STD_LOGIC;
482 signal m_axis_aresetn : STD_LOGIC;
483 --signal header_reg : std_logic_vector(95 downto 0) := x"000000000000000000000000";
484 signal tvalid_prev : STD_LOGIC := '0';
485 signal first_cyc : STD_LOGIC;
486 --signal header_marker : STD_LOGIC;
487 --signal tail_marker : STD_LOGIC;
488 signal poll_reg : STD_LOGIC := '0';
489 
490 signal len_count : STD_LOGIC_VECTOR (11 downto 0);
491 signal frag_length : STD_LOGIC_VECTOR (11 downto 0);
492 signal t_last_delay : STD_LOGIC;
493 signal no_complete_frag : STD_LOGIC;
494 signal m_fifo_tlast : STD_LOGIC;
495 signal rd_len_fifo : STD_LOGIC;
496 signal hdr_length : STD_LOGIC_VECTOR ((length_msb - length_lsb) downto 0);
497 signal length_error : STD_LOGIC;
498 --signal tkeep_in : STD_LOGIC_VECTOR (2 downto 0);
499 --signal tkeep_in : STD_LOGIC_VECTOR (1 downto 0);
500 --signal tval_tob : STD_LOGIC;
501 signal pipe_m_tval_tob : STD_LOGIC;
502 signal tob_fifo_en : STD_LOGIC;
503 --signal tval_calo : STD_LOGIC;
504 signal pipe_m_tval_calo : STD_LOGIC;
505 signal calo_fifo_en : STD_LOGIC;
506 signal calo_fifo_tvalid : STD_LOGIC;
507 signal tob_fifo_tvalid : STD_LOGIC;
508 signal tob_axis_rd_data_count : STD_LOGIC_VECTOR (31 downto 0);
509 signal tob_axis_wr_data_count : STD_LOGIC_VECTOR (31 downto 0);
510 
511 signal calo_axis_data_count : STD_LOGIC_VECTOR (31 downto 0);
512 signal calo_axis_wr_data_count : STD_LOGIC_VECTOR (31 downto 0);
513 signal calo_axis_rd_data_count : STD_LOGIC_VECTOR (31 downto 0);
514 
515 signal calo_int_axis_tready : STD_LOGIC;
516 signal calo_poll_reg : STD_LOGIC := '0';
517 signal calo_header_marker_i : std_logic;
518 signal calo_tail_marker_i : std_logic;
519 
520 
521 signal cc_int_axis_tready_i : STD_LOGIC;
522 signal cc_poll_reg : STD_LOGIC := '0';
523 signal tob_header_marker_i : std_logic;
524 signal tob_tail_marker_i : std_logic;
525 
526 signal cc_tob_fifo_en : std_logic;
527 --signal cc_tob_fifo_tvalid : std_logic;
528 signal s_axis_tready_i : std_logic;
529 signal m_tvalid_i : std_logic;
530 
531 signal tob_trans : std_logic;
532 signal tob_buf_tvalid : std_logic;
533 
534 signal calo_s_axis_tready_i : std_logic;
535 signal calo_m_tvalid_i : std_logic;
536 signal calo_m_fifo_tlast_i : std_logic;
537 signal calo_m_axis_tdata_i : std_logic_vector (63 downto 0);
538 
539 signal fifo_vio_reset : std_logic;
540 signal reset_i : std_logic;
541 signal RESET_stretch_i : std_logic;
542 
543 signal tob_fifo_reset : std_logic;
544 signal bulk_fifo_reset : std_logic;
545 signal n_tob_fifo_reset : std_logic;
546 signal n_bulk_fifo_reset : std_logic;
547 signal aurora_channel_control_i : STD_LOGIC_VECTOR (31 downto 0);
548 
549 signal pipe_m_axis_tvalid : std_logic;
550 signal pipe_m_axis_tlast : std_logic;
551 signal pipe_m_axis_tdata : std_logic_vector (63 downto 0);
552 signal pipe_m_first_cyc : std_logic;
553 signal s_crc_error : std_logic;
554 signal m_crc_error : std_logic;
555 signal tob_m_axis_tuser : std_logic_vector (3 downto 0);
556 signal calo_m_axis_tuser : std_logic_vector (3 downto 0);
557 signal crc_tag : std_logic;
558 signal hdr_crc_tag_i : std_logic;
559 signal pkt_len_violation : STD_LOGIC;
560 
561 signal ufc_message : STD_LOGIC_Vector(7 downto 0);
562 signal ufc_parity_error : STD_LOGIC;
563 signal ufc_channel_busy : STD_LOGIC;
564 signal ufc_parity_disable : std_logic;
565 signal test_signal : STD_LOGIC;
566 
567 signal comb_error : STD_logic;
568 signal pipe_m_comb_error : STD_LOGIC;
569 
570 signal last_l1id : STD_LOGIC_vector(31 downto 0);
571 signal current_l1id : STD_LOGIC_vector(31 downto 0);
572 signal first_event : STD_LOGIC;
573 signal repeat_l1id_counter : STD_LOGIC_vector(31 downto 0);
574 signal repeat_l1id_counter_reset : STD_LOGIC;
575 signal packets_read_counter : STD_LOGIC_vector(31 downto 0);
576 signal packets_read_counter_reset : STD_LOGIC;
577 
578 begin
579 
580 --work in progress-------------
581 aurora_channel_control <= aurora_channel_control_i;
582 
583 tob_fifo_reset <= aurora_channel_control_i(3) or RESET;
584 bulk_fifo_reset <= aurora_channel_control_i(4) or RESET;
585 
586 n_tob_fifo_reset <= not tob_fifo_reset;
587 n_bulk_fifo_reset <= not bulk_fifo_reset;
588 --maybe there should be one reset for both TOB and Bulk: if one is messed up, probably the other is too - also cc_poll_reg doesn't have reset?
589 
590 comb_error <= aurora_chan_stat(8) or aurora_chan_stat(9) or aurora_chan_stat(10) or aurora_chan_stat(11) or not aurora_chan_stat(0);
591 
592 --work in progress-------------
593 
594 
595 
596 --s_axis_aresetn <= not RESET_i;
597 --m_axis_aresetn <= not RESET_i;
598 
599 s_axis_aresetn <= not RESET_stretch_i;
600 m_axis_aresetn <= not RESET_stretch_i;
601 
602 
603 
604 --This pulse stretcher changed to pp_clock because aurora_user_clk can stop during reset! The output will be asynch to the
605 --pipeline, but this should be OK since it lasts several cycles. On the trailing edge the reg inputs will all be zero
606 pulse_stretcher : pulse_stretch
607  generic map (
608  COUNTER_WIDTH => 8
609  )
610  Port map (
611 -- clock => aurora_user_clk,
612  clock => pp_clock, --changed to pp_clock because aurora_user_clk can stop during reset!
613  reset => '0',
614  pulse_in => RESET_i,
615  pulse_out => Reset_stretch_i
616  );
617 
618 tob_s_tready <= s_axis_tready_i;
619 tob_m_tvalid <= m_tvalid_i;
620 
621 input_pipe : aurora_pipe
622  generic map (
623  channel_num => channel_num,
624  lmem => lmem,
625  max_packet_length => max_packet_length
626  )
627  Port map (
628  pp_clock => pp_clock,
629  aurora_user_clk => aurora_user_clk,
630  reset => reset_stretch_i,
631  aurora_chan_stat => aurora_chan_stat,
632  s_axis_tvalid => s_axis_tvalid,
633  s_axis_tlast => s_axis_tlast,
634  s_axis_tdata => s_axis_tdata,
635  m_axis_tvalid => pipe_m_axis_tvalid,
636  m_axis_tlast => pipe_m_axis_tlast,
637  m_first_cyc => pipe_m_first_cyc,
638  m_tval_tob => pipe_m_tval_tob,
639  m_tval_calo => pipe_m_tval_calo,
640  m_axis_tdata => pipe_m_axis_tdata,
641  crc_error => s_crc_error,
642  pkt_len_violation => pkt_len_violation,
643  comb_error => comb_error,
644  m_comb_error => pipe_m_comb_error
645  );
646 --crc_tag <= s_crc_error AND first_cyc;
647 
648 hdr_crc_tag_i <= tob_m_axis_tuser(2) AND tob_m_axis_tuser(0);
649 hdr_crc_tag <= hdr_crc_tag_i;
650 comb_error_tag <= tob_m_axis_tuser(3);
651 
652 norm_fifo: if axi_fifo=0 generate
653 --clk_cross_tob_fifo : clock_cross_fifo
654 
655 no_fifo_ila: if ((fifo_instr = 0) or (jfex = 0)) generate
656 
657 clk_cross_tob_fifo : dual_input_fifo_4k
658  PORT MAP (
659 -- wr_rst_busy => open,
660 -- rd_rst_busy => open,
661  m_aclk => pp_clock,
662  s_aclk => aurora_user_clk,
663  s_aresetn => s_axis_aresetn,
664  -- s_axis_tvalid => s_axis_tvalid,
665  s_axis_tvalid => tob_fifo_tvalid,
666  s_axis_tready => s_axis_tready_i,
667  s_axis_tdata => pipe_m_axis_tdata,
668  s_axis_tlast => pipe_m_axis_tlast,
669  s_axis_tuser(0) => first_cyc,
670  s_axis_tuser(1) => pipe_m_axis_tlast,
671  s_axis_tuser(2) => s_crc_error,
672  s_axis_tuser(3) => pipe_m_comb_error,
673  m_axis_tvalid => m_tvalid_i,
674  m_axis_tready => cc_int_axis_tready_i,
675  m_axis_tdata => tob_m_axis_tdata,
676  m_axis_tlast => m_fifo_tlast,
677  m_axis_tuser => tob_m_axis_tuser,
678 -- m_axis_tuser(0) => tob_header_marker_i,
679 -- m_axis_tuser(1) => tob_tail_marker_i,
680 -- m_axis_tuser(2) => m_crc_error,
681 -- m_axis_tuser(3) => m_axis_tuser(3),
682 -- axis_wr_data_count => tob_axis_wr_data_count(11 downto 0),
683 -- axis_rd_data_count => tob_axis_rd_data_count(11 downto 0)
684  axis_wr_data_count => tob_axis_wr_data_count(31 downto 0),
685  axis_rd_data_count => tob_axis_rd_data_count(31 downto 0)
686 -- axis_prog_full => open
687 
688  );
689 
690 end generate no_fifo_ila;
691 
692 fifo_ila: if ((fifo_instr = 1) and (jfex = 1)) generate
693 clk_cross_tob_fifo : jfex_test_fifo_2 --jfex_test_input_fifo
694  PORT MAP (
695 -- wr_rst_busy => open,
696 -- rd_rst_busy => open,
697  m_aclk => pp_clock,
698  s_aclk => aurora_user_clk,
699  s_aresetn => s_axis_aresetn,
700  -- s_axis_tvalid => s_axis_tvalid,
701  s_axis_tvalid => tob_fifo_tvalid,
702  s_axis_tready => s_axis_tready_i,
703  s_axis_tdata => pipe_m_axis_tdata,
704  s_axis_tlast => pipe_m_axis_tlast,
705  s_axis_tuser(0) => first_cyc,
706  s_axis_tuser(1) => pipe_m_axis_tlast,
707  s_axis_tuser(2) => s_crc_error,
708  s_axis_tuser(3) => pipe_m_comb_error,
709  m_axis_tvalid => m_tvalid_i,
710  m_axis_tready => cc_int_axis_tready_i,
711  m_axis_tdata => tob_m_axis_tdata,
712  m_axis_tlast => m_fifo_tlast,
713  m_axis_tuser => tob_m_axis_tuser,
714 -- m_axis_tuser(0) => tob_header_marker_i,
715 -- m_axis_tuser(1) => tob_tail_marker_i,
716 -- m_axis_tuser(2) => m_crc_error,
717 -- m_axis_tuser(3) => m_axis_tuser(3),
718 -- axis_wr_data_count => tob_axis_wr_data_count(11 downto 0),
719 -- axis_rd_data_count => tob_axis_rd_data_count(11 downto 0)
720  axis_wr_data_count => tob_axis_wr_data_count(31 downto 0),
721  axis_rd_data_count => tob_axis_rd_data_count(31 downto 0),
722 -- axis_prog_full => open
723  timeout_err => timeout_err
724  );
725 
726 end generate fifo_ila;
727 
728 
729 
730 
731 --calo_fifo : axis_data_fifo_in
732 --calo_fifo : clock_cross_fifo
733 calo_fifo : dual_input_fifo_4k
734  PORT MAP (
735 -- wr_rst_busy => open,
736 -- rd_rst_busy => open,
737  m_aclk => pp_clock,
738  s_aclk => aurora_user_clk,
739 -- s_axis_aresetn => s_axis_aresetn,
740  s_aresetn => s_axis_aresetn,
741 -- m_axis_aresetn => m_axis_aresetn,
742 -- s_axis_aclk => pp_clock,
743 -- s_axis_aclk => aurora_user_clk,
744  s_axis_tvalid => calo_fifo_tvalid,
745  s_axis_tready => calo_s_axis_tready_i,
746  s_axis_tdata => pipe_m_axis_tdata,
747  s_axis_tlast => pipe_m_axis_tlast,
748 -- s_axis_tuser => s_axis_tuser,
749  s_axis_tuser(0) => pipe_m_first_cyc,
750  s_axis_tuser(1) => pipe_m_axis_tlast,
751  s_axis_tuser(2) => '0',
752  s_axis_tuser(3) => '0',
753 -- m_axis_aclk => pp_clock,
754  m_axis_tvalid => calo_m_tvalid_i,
755  m_axis_tready => calo_int_axis_tready,
756  m_axis_tdata => calo_m_axis_tdata_i,
757  m_axis_tlast => calo_m_fifo_tlast_i,
758  m_axis_tuser => calo_m_axis_tuser,
759 -- m_axis_tuser(0) => calo_header_marker_i,
760 -- m_axis_tuser(1) => calo_tail_marker_i,
761 -- axis_data_count => calo_axis_data_count,
762  axis_wr_data_count => calo_axis_wr_data_count(31 downto 0),
763  axis_rd_data_count => calo_axis_rd_data_count(31 downto 0)
764  );
765 end generate norm_fifo;
766 
767 axi_type_fifo: if axi_fifo=1 generate
768 
769 clk_cross_tob_fifo : axis_input_fifo
770  PORT MAP (
771  s_axis_aresetn => s_axis_aresetn,
772  s_axis_aclk => aurora_user_clk,
773  s_axis_tvalid => tob_fifo_tvalid,
774  s_axis_tready => s_axis_tready_i,
775  s_axis_tdata => pipe_m_axis_tdata,
776  s_axis_tlast => pipe_m_axis_tlast,
777  s_axis_tuser(0) => pipe_m_first_cyc,
778  s_axis_tuser(1) => pipe_m_axis_tlast,
779  s_axis_tuser(2) => s_crc_error,
780  s_axis_tuser(3) => pipe_m_comb_error,
781  m_axis_aclk => pp_clock,
782  m_axis_tvalid => m_tvalid_i,
783  m_axis_tready => cc_int_axis_tready_i,
784  m_axis_tdata => tob_m_axis_tdata,
785  m_axis_tlast => m_fifo_tlast,
786  m_axis_tuser => tob_m_axis_tuser,
787  axis_wr_data_count => tob_axis_wr_data_count,
788  axis_rd_data_count => tob_axis_rd_data_count
789 
790  );
791 
792 calo_fifo : axis_input_fifo
793  PORT MAP (
794  s_axis_aresetn => s_axis_aresetn,
795  s_axis_aclk => aurora_user_clk,
796  s_axis_tvalid => calo_fifo_tvalid,
797  s_axis_tready => calo_s_axis_tready_i,
798  s_axis_tdata => pipe_m_axis_tdata,
799  s_axis_tlast => pipe_m_axis_tlast,
800  s_axis_tuser(0) => pipe_m_first_cyc,
801  s_axis_tuser(1) => pipe_m_axis_tlast,
802  s_axis_tuser(2) => '0',
803  s_axis_tuser(3) => '0',
804  m_axis_aclk => pp_clock,
805  m_axis_tvalid => calo_m_tvalid_i,
806  m_axis_tready => calo_int_axis_tready,
807  m_axis_tdata => calo_m_axis_tdata_i,
808  m_axis_tlast => calo_m_fifo_tlast_i,
809  m_axis_tuser => calo_m_axis_tuser,
810  axis_wr_data_count => calo_axis_wr_data_count,
811  axis_rd_data_count => calo_axis_rd_data_count
812  );
813 
814 end generate axi_type_fifo;
815 
816 tob_header_marker_i <= tob_m_axis_tuser(0);
817 tob_tail_marker_i <= tob_m_axis_tuser(1);
818 m_crc_error <= tob_m_axis_tuser(2);
819 --m_comb_error <= tob_m_axis_tuser(3);
820 
821 
822 chan_dbg: if debug=1 generate
823 tob_fifo_in_ila : aurora_fifo_in_ila
824 PORT MAP (
825  clk => aurora_user_clk,
826 -- probe0(0) => s_axis_tvalid,
827  probe0(0) => pipe_m_axis_tvalid,
828  probe1(0) => tob_fifo_tvalid,
829  probe2(0) => pipe_m_axis_tlast,
830 -- probe3 => s_axis_tdata,
831  probe3 => pipe_m_axis_tdata,
832  probe4(0) => s_axis_tready_i,
833  probe5(0) => pipe_m_first_cyc,
834  probe6(0) => tob_trans,
835  probe7(0) => pipe_m_tval_tob,
836  probe8(0) => pipe_m_axis_tdata(7),
837  probe9(0) => first_cyc,
838  probe10(0) => pipe_m_tval_calo,
839  probe11(0) => calo_fifo_tvalid,
840  probe12(0) => s_crc_error,
841  probe13 => (others => '0'),
842  probe14 => (others => '0'),
843  probe15 => (others => '0'),
844  probe16 => (others => '0')
845 
846 );
847 
848 
849 tob_fifo_out_ila : aurora_fifo_out_ila
850 PORT MAP (
851  clk => pp_clock,
852  probe0(0) => m_tvalid_i,
853  probe1(0) => m_fifo_tlast,
854  probe2(0) => cc_int_axis_tready_i,
855  probe3 => tob_m_axis_tdata,
856  probe4(0) => tob_header_marker_i,
857  probe5(0) => tob_tail_marker_i,
858  probe6(0) => s_axis_tready_i,
859  probe7 => tob_axis_rd_data_count(10 downto 0),
860  probe8 => tob_axis_wr_data_count(10 downto 0),
861 -- probe9(0) => tob_axis_prog_full
862  probe9(0) => hdr_crc_tag_i
863 );
864 
865 calo_fifo_out_ila : aurora_fifo_out_ila
866 PORT MAP (
867  clk => pp_clock,
868  probe0(0) => calo_m_tvalid_i,
869  probe1(0) => calo_m_fifo_tlast_i,
870  probe2(0) => calo_int_axis_tready,
871  probe3 => calo_m_axis_tdata_i,
872  probe4(0) => calo_header_marker_i,
873  probe5(0) => calo_tail_marker_i,
874  probe6(0) => calo_s_axis_tready_i,
875  probe7 => calo_axis_rd_data_count(10 downto 0),
876  probe8 => calo_axis_wr_data_count(10 downto 0),
877  probe9(0) => hdr_crc_tag_i
878 );
879 
880 
881 
882 
883 channel_fifo_vio: data_fifo_vio
884  PORT MAP (
885  clk => pp_clock,
886  probe_in0(0) => reset_stretch_i,
887  probe_out0(0) => fifo_vio_reset
888  );
889 end generate chan_dbg;
890 
891 chan_no_dbg: if debug=0 generate
892 fifo_vio_reset <= '0';
893 end generate chan_no_dbg;
894 
895 
896 --reset_i <= reset or fifo_vio_reset or aurora_channel_control_i(30) ; --2021_05_05 added processor reset: backplane conetrol(5)
897 --reset_i <= reset or fifo_vio_reset or aurora_channel_control(3) or aurora_channel_control(4) or backplane_control(5);
898 reset_i <= reset or wdog_fifo_reset or fifo_vio_reset or aurora_channel_control(3) or aurora_channel_control(4) or backplane_control(5) or backplane_control(31); --added input hold control
899 
900 
901 
902  calo_header_marker_i <= calo_m_axis_tuser(0);
903  calo_tail_marker_i <= calo_m_axis_tuser(1);
904 
905 calo_m_tvalid <= calo_m_tvalid_i;
906 calo_s_axis_tready <= calo_s_axis_tready_i;
907 calo_m_fifo_tlast <= calo_m_fifo_tlast_i;
908 calo_m_axis_tdata <= calo_m_axis_tdata_i;
909 
910 -- it's the first cycle if tvalid has just risen, or if the previous cycle was tlast and tvalid is still high.
911 
912 process (aurora_user_clk) begin
913  if rising_edge (aurora_user_clk) then
914  tvalid_prev <= (not pipe_m_axis_tvalid) or (pipe_m_axis_tlast and pipe_m_axis_tvalid);
915  end if;
916  end process;
917 
918 
919 first_cyc <= pipe_m_axis_tvalid and tvalid_prev and not pipe_m_axis_tlast and not tob_trans and not calo_fifo_en;
920 
921 --decide if this packet is TOBS or Calo bulk data
922 -- for TOBS, the stream id = x"01"
923 -- for bulk, the stream id = x"40" (or above?)
924 
925 -- note: this decoding is current done from the last stage of the pipe. However, it could be moved back one stage
926 -- to improve timing. If decoding becomes more complex, this will be necessary
927 
928 
929 -- tval_tob <= first_cyc;
930 -- tval_tob <= first_cyc and pipe_m_axis_tdata(0) and not pipe_m_axis_tdata(1);
931 --24-Nov-19
932 -- tval_tob <= pipe_m_first_cyc and pipe_m_axis_tdata(0) and not pipe_m_axis_tdata(1);
933 
934 
935  --clock crossing TOB fifo tvalid
936  process (aurora_user_clk) begin
937  if rising_edge (aurora_user_clk) then
938  if (pipe_m_tval_tob = '1') and (pipe_m_axis_tlast = '0') and (RESET_stretch_i = '0') then
939  tob_trans <= '1';
940  elsif (((pipe_m_axis_tvalid and pipe_m_axis_tlast) = '1') or (RESET_stretch_i = '1')) then
941  tob_trans <= '0';
942  else
943  tob_trans <= tob_trans;
944  end if;
945  end if;
946  end process;
947 
948 --------temporary experiment----------------
949  -------attempting to remove one layer of logic by eliminating tval_tob
950 -- tob_fifo_tvalid <= (tval_tob OR tob_trans) AND pipe_m_axis_tvalid;
951 tob_fifo_tvalid <= (pipe_m_tval_tob OR tob_trans) AND pipe_m_axis_tvalid;
952  --tob_fifo_tvalid <= ((tvalid_prev and not pipe_m_axis_tlast and not tob_trans and not calo_fifo_en) OR tob_trans) AND pipe_m_axis_tvalid;
953  --------------------end of temporary experiment -------------------------
954 
955 
956 
957 
958  -- for calo bulk data
959  -- tval_calo <= first_cyc and pipe_m_axis_tdata(6) and not s_crc_error;
960  --24-Nov-19
961  -- tval_calo <= pipe_m_first_cyc and pipe_m_axis_tdata(6) and not s_crc_error;
962 
963  process (aurora_user_clk) begin
964  if rising_edge (aurora_user_clk) then
965  if (pipe_m_tval_calo = '1') and (pipe_m_axis_tlast = '0')and (RESET_stretch_i = '0') then
966  calo_fifo_en <= '1';
967  elsif (((pipe_m_axis_tvalid and pipe_m_axis_tlast) = '1') or (RESET_stretch_i = '1')) then
968  calo_fifo_en <= '0';
969  else
970  calo_fifo_en <= calo_fifo_en;
971  end if;
972  end if;
973  end process;
974 
975  --calo_fifo_tvalid <= (calo_fifo_en or tval_calo) AND pipe_m_axis_tvalid;
976  calo_fifo_tvalid <= (calo_fifo_en or pipe_m_tval_calo) AND pipe_m_axis_tvalid;
977 
978 
979 
980 
981 
982  process (pp_clock) begin
983  if rising_edge (pp_clock) then
984  if (tob_header_marker_i = '1') and (poll_chan = '1') then
985  cc_poll_reg <= '1';
986  elsif (RESET_stretch_i = '1') or ((cc_poll_reg = '1') and (tob_tail_marker_i = '1')) then
987  cc_poll_reg <= '0';
988  end if;
989  end if;
990  end process;
991 
992 
993 
994 process (pp_clock) begin
995  if rising_edge (pp_clock) then
996  if (calo_header_marker_i = '1') and (calo_poll_chan = '1') then
997  calo_poll_reg <= '1';
998  elsif (RESET_stretch_i = '1') or ((calo_poll_reg = '1') and (calo_tail_marker_i = '1')) then
999  calo_poll_reg <= '0';
1000  end if;
1001  end if;
1002  end process;
1003 
1004 
1005 
1006 
1007 
1008 
1009 
1010 
1011  process (aurora_user_clk) begin
1012  if rising_edge (aurora_user_clk) then
1013  if (pipe_m_axis_tvalid = '1') and (pipe_m_axis_tlast = '1') and (reset_stretch_i ='0') then
1014  t_last_delay <= '1';
1015  else
1016  t_last_delay <= '0';
1017  end if;
1018  end if;
1019  end process;
1020 
1021 
1022 
1023 
1024 
1025 
1026 
1027  --revised lencount which doesn't use TKEEP 22/07/2018
1028 -- process (aurora_user_clk)
1029 -- begin
1030 -- if rising_edge (aurora_user_clk) then
1031 -- if (reset = '1') or (t_last_delay = '1') then
1032 -- len_count <= "000000000000";
1033 -- elsif (s_axis_tvalid = '1') then
1034 -- len_count <= (len_count + 2);
1035 -- end if;
1036 -- end if;
1037 -- end process;
1038 
1039 
1040 
1041 -----length error flag -------------------------
1042  process (pp_clock) begin
1043  if rising_edge (pp_clock) then
1044  if (reset_stretch_i = '1')or ((tob_header_marker_i = '1') and (frag_length = hdr_length) and (no_complete_frag = '0')) then
1045  length_error <= '0';
1046  elsif (tob_header_marker_i = '1') and (frag_length /= hdr_length) and (no_complete_frag = '0') then
1047  length_error <= '1';
1048  end if;
1049  end if;
1050  end process;
1051 
1052 
1053 
1054 ---------end of fragment length measurement ---------------------------------
1055 ----------------------------------------------------------------------------
1056 
1057 
1058  hdr_length <= tob_m_axis_tdata(length_msb downto length_lsb);
1059  current_l1id <= tob_m_axis_tdata(63 downto 32);
1060 
1061  tob_m_tlast <= m_fifo_tlast;
1062  tob_m_tdata <= tob_m_axis_tdata;
1063 
1064 calo_int_axis_tready <= (not (calo_header_marker_i and not calo_poll_reg)) and calo_m_axis_tready;
1065 
1066 calo_header_marker <= calo_header_marker_i;
1067 calo_tail_marker <= calo_tail_marker_i;
1068 
1069 --cc_int_axis_tready_i <= not (tob_header_marker_i and not cc_poll_reg);
1070 cc_int_axis_tready_i <= (not (tob_header_marker_i and not cc_poll_reg)) and tob_m_tready;
1071 tob_header_marker <= tob_header_marker_i;
1072 tob_tail_marker <= tob_tail_marker_i;
1073 
1074 
1075 ufc_receiver : ufc_rx
1076  Port map (
1077  clock => aurora_user_clk,
1078  reset => reset_stretch_i,
1079  axi_ufc_rx_tvalid => s_axi_ufc_rx_tvalid,
1080  axi_ufc_rx_tlast => s_axi_ufc_rx_tlast,
1081  axi_ufc_rx_tdata => s_axi_ufc_rx_tdata(15 downto 0),
1082 
1083  ufc_message => ufc_message,
1084  ufc_parity_error => ufc_parity_error,
1085  ufc_parity_disable => ufc_parity_disable,
1086  ufc_channel_Busy => ufc_channel_busy
1087 
1088  );
1089 
1090 
1091 --channel_busy <= ufc_channel_busy; --or local busy
1092 
1093 
1094 --capture the last_l1ID ------
1095 
1096 process (pp_clock) begin
1097  if rising_edge (pp_clock) then
1098  if reset = '1' then
1099  last_l1id <= (others=> '0');
1100  elsif (poll_chan = '1') then
1101  last_l1id <= current_l1id;
1102  end if;
1103  end if;
1104 end process;
1105 
1106 --flag the first event with l1id = 00000000
1107 process (pp_clock) begin
1108  if rising_edge (pp_clock) then
1109  if reset = '1' then
1110  first_event <= '1';
1111  elsif (poll_chan = '1') then
1112  first_event <= '0';
1113  end if;
1114  end if;
1115 end process;
1116 
1117 --increment error counter on duplicate l1id
1118 process (pp_clock) begin
1119  if rising_edge (pp_clock) then
1120  if (reset = '1') or (repeat_l1id_counter_reset = '1') then
1121  repeat_l1id_counter <= (others => '0');
1122  elsif (poll_chan = '1') and (current_L1id = last_l1id) and (first_event = '0') and (repeat_l1id_counter <= x"ffffffff") then
1123  repeat_l1id_counter <= (repeat_l1id_counter + '1');
1124  end if;
1125  end if;
1126 end process;
1127 
1128 
1129 --count the number of packets read from the fifo
1130 process (pp_clock) begin
1131  if rising_edge (pp_clock) then
1132  if (reset = '1') or (packets_read_counter_reset = '1') then
1133  packets_read_counter <= (others => '0');
1134  elsif (poll_chan = '1') and (packets_read_counter <= x"ffffffff") then
1135  packets_read_counter <= (packets_read_counter + '1');
1136  end if;
1137  end if;
1138 end process;
1139 
1140 
1141 
1142 ------------------------------------------------------
1143 --------IPBUS--------------------
1144 
1145 gen_reg: if SIM=0 generate
1146 status_regs : fex_chan_regs
1147  generic map (
1148  jfex => jfex
1149  )
1150  port map (
1151  ipb_clk => ipb_clk,
1152  ipb_rst => ipb_rst,
1153  ipb_in => ipb_in,
1154  ipb_out => ipb_out,
1155 
1156  pp_clock => pp_clock,
1157  clk_160 => clk_160,
1158  rt_clk => rt_clk,
1159 
1160  aurora_user_clk => aurora_user_clk,
1161  aurora_chan_stat => aurora_chan_stat,
1162  tob_fifo_level => tob_axis_rd_data_count(15 downto 0),
1163  bulk_fifo_level => calo_axis_rd_data_count(15 downto 0),
1164 
1165  time_count => time_count,
1166  tob_fifo_busy_threshold => tob_fifo_busy_threshold,
1167  bulk_fifo_busy_threshold => bulk_fifo_busy_threshold,
1168  tob_fifo_xoff_threshold => tob_fifo_xoff_threshold,
1169  bulk_fifo_xoff_threshold => bulk_fifo_xoff_threshold,
1170 
1171  hdr_crc_tag => hdr_crc_tag_i,
1172 
1173  aurora_channel_control => aurora_channel_control_i,
1174  chan_disable => chan_disable,
1175  init_clk => init_clk,
1176  bp_reg_reset => bp_reg_reset,
1177  master_reset => master_reset,
1178  pkt_len_violation => pkt_len_violation,
1179 
1180  --ufc message axi bus --------------------------------------
1181 -- s_axi_ufc_rx_tdata => s_axi_ufc_rx_tdata,
1182 -- s_axi_ufc_rx_tvalid => s_axi_ufc_rx_tvalid,
1183 -- s_axi_ufc_rx_tlast => s_axi_ufc_rx_tlast
1184  ufc_message => ufc_message,
1185  ufc_parity_error => ufc_parity_error,
1186  ufc_channel_busy => ufc_channel_busy,
1187  ufc_parity_disable => ufc_parity_disable,
1188  channel_busy => channel_busy,
1189 
1190 
1191  L1A => L1A,
1192  s_tvalid => m_tvalid_i,
1193 
1194  repeat_l1id_counter => repeat_l1id_counter,
1195  repeat_l1id_counter_reset => repeat_l1id_counter_reset,
1196  packets_read_counter => packets_read_counter,
1197  packets_read_counter_reset => packets_read_counter_reset
1198 
1199 -- cfifo_xoff_ena => open,
1200 -- tfifo_xoff_ena => open,
1201 
1202 
1203 -- stat_reg_out => open
1204 -- ctrl_out => open
1205 
1206  );
1207 
1208 end generate gen_reg;
1209 
1210 gen_sim: if SIM=1 generate
1211 
1212 channel_busy <= ufc_channel_busy;
1213 --aurora_channel_control_i(3) <= '0';
1214 --aurora_channel_control_i(4) <= '0';
1215 
1216 end generate gen_sim;
1217 
1218 
1219 end RTL;
aurora_pipe
Definition: aurora_pipe.vhd:35
channel_fifo.RTL
Definition: channel_fifo.vhd:202
channel_fifo
--------------------------------------------------- Backplane Control Bus bit Definitions -----------...
Definition: channel_fifo.vhd:94
dual_input_fifo_4k
Definition: dual_input_fifo_4k.vhd:34
fex_chan_regs
Definition: fex_chan_regs.vhd:46
jfex_test_fifo_2
Definition: jfex_test_fifo_2.vhd:35
pulse_stretch
Definition: pulse_stretch.vhd:35
ufc_rx
Definition: ufc_rx.vhd:54
Generated on Sat Dec 14 2024 13:33:14 for ROD firmware by   doxygen 1.9.1