aurora_pipe.vhd

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 29.07.2019 12:46:52
-- Design Name: 
-- Module Name: aurora_pipe - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity aurora_pipe is
    generic (
           channel_num      : STD_LOGIC_VECTOR (11 downto 0)    := "000000000000";
           lmem             : STD_LOGIC_VECTOR (3 downto 0)     := "0000";
           max_packet_length : STD_LOGIC_VECTOR (15 downto 0)   := x"02A0"            
          );    
    
    Port ( pp_clock       : in STD_LOGIC;
           aurora_user_clk : in STD_LOGIC;
           reset        : in STD_LOGIC;
           aurora_chan_stat : in STD_LOGIC_VECTOR (31 downto 0);
           s_axis_tvalid : in STD_LOGIC;
           s_axis_tlast  : in STD_LOGIC;
           s_axis_tdata  : in STD_LOGIC_VECTOR (63 downto 0);
           m_axis_tvalid : out STD_LOGIC;
           m_axis_tlast  : out STD_LOGIC;
           m_axis_tdata  : out STD_LOGIC_VECTOR (63 downto 0);
           m_first_cyc   : out STD_LOGIC;
           crc_error     : out STD_LOGIC;
           m_tval_tob    : out STD_LOGIC;
           m_tval_calo   : out STD_LOGIC; 
           pkt_len_violation : out STD_LOGIC;
          
           comb_error    : in STD_LOGIC;
           m_comb_error  : out std_logic         
                  
           );
end aurora_pipe;
 
architecture RTL of aurora_pipe is
 
component CRC 
   generic(
     Nbits :  positive  := 64;
     CRC_Width        :  positive   := 9;
--     G_Poly: Std_Logic_Vector :=x"17d";
     --G_Poly: Std_Logic_Vector := "101111101";
     G_Poly: Std_Logic_Vector :=   "011111011";
     G_InitVal: std_logic_vector:= "111111111"
     );
   port(
  CRC   : out    std_logic_vector(CRC_Width-1 downto 0);
  Calc  : in     std_logic;
  Clk   : in     std_logic;
  DIn   : in     std_logic_vector(Nbits-1 downto 0);
  Reset : in     std_logic);
end component;
 
 
component pulse_stretch is
    generic (
 COUNTER_WIDTH  : integer :=   7       
   );    
    Port ( 
          clock : in STD_LOGIC;
          reset :  in STD_LOGIC;
          pulse_in : in STD_LOGIC;
          pulse_out : out STD_LOGIC
                   
          );
end component;
 
 
signal   axis_tvalid_1 : STD_LOGIC  := '0';
signal   axis_tlast_1  : STD_LOGIC  := '0';
signal   axis_tdata_1  : STD_LOGIC_VECTOR (63 downto 0);
signal   first_cyc_1    :  STD_LOGIC   := '0';
signal   comb_error_1    :  STD_LOGIC   := '0';
 
signal   axis_tvalid_2 : STD_LOGIC     := '0';
signal   axis_tlast_2  : STD_LOGIC     := '0';
signal   axis_tdata_2  : STD_LOGIC_VECTOR (63 downto 0);
signal   first_cyc_2    :  STD_LOGIC   := '0';
signal   comb_error_2    :  STD_LOGIC   := '0';
 
signal   axis_tvalid_3  : STD_LOGIC  := '0'; 
signal   axis_tlast_3   : STD_LOGIC  := '0'; 
signal   axis_tdata_3   : STD_LOGIC_VECTOR (63 downto 0); 
signal   first_cyc_3    : STD_LOGIC  := '0';
signal   comb_error_3    :  STD_LOGIC   := '0';
signal   tval_tob_3     : STD_LOGIC  := '0';
signal   tval_calo_3    : STD_LOGIC  := '0';
 
signal   axis_tvalid_4  : STD_LOGIC  := '0'; 
signal   axis_tlast_4   : STD_LOGIC  := '0'; 
signal   axis_tdata_4   : STD_LOGIC_VECTOR (63 downto 0); 
signal   first_cyc_4    : STD_LOGIC  := '0';
signal   comb_error_4    :  STD_LOGIC   := '0';
signal   tval_tob_4     : STD_LOGIC  := '0';
signal   tval_calo_4    : STD_LOGIC  := '0';
 
signal   m_axis_tvalid_i : STD_LOGIC   := '0'; 
signal   m_axis_tlast_i  : STD_LOGIC    := '0';
signal   m_axis_tdata_i  : STD_LOGIC_VECTOR (63 downto 0);
signal   m_first_cyc_i    :  STD_LOGIC   := '0';
signal   s_first_cyc    :  STD_LOGIC;
signal   tvalid_prev  : STD_LOGIC      := '0';
signal   generated_crc: STD_LOGIC_VECTOR (8 downto 0);
signal   header_crc   : STD_LOGIC_VECTOR (8 downto 0);
signal   crc_error_i    : STD_LOGIC;
signal   crc_error_3    : STD_LOGIC      := '0';
signal   crc_error_4    : STD_LOGIC      := '0';
signal   crc_input_low : STD_LOGIC_VECTOR (31 downto 0);
signal   crc_input_high : STD_LOGIC_VECTOR (31 downto 0);
signal   crc_input_flip : STD_LOGIC_VECTOR (63 downto 0);
signal   m_tval_tob_i    : STD_LOGIC      := '0';
signal   tval_tob       : STD_LOGIC      := '0';
signal   m_tval_calo_i  : STD_LOGIC      := '0'; 
signal   tval_calo      : STD_LOGIC      := '0';
 
signal pkt_count       : STD_LOGIC_VECTOR (15 downto 0)    := x"0000"; 
signal trailer_value   : STD_LOGIC_VECTOR (63 downto 0);
signal terminate_pkt   : STD_LOGIC      := '0'; 
signal terminate_pkt_1   : STD_LOGIC      := '0';
signal terminate_pkt_2   : STD_LOGIC      := '0';  
signal terminate_pkt_flag   : STD_LOGIC      := '0'; 
signal pkt_len_violation_i : STD_LOGIC      := '0'; 
signal in_progress         : STD_LOGIC;
 
signal calc_crc20          : STD_LOGIC;
signal generated_crc20     : STD_LOGIC_vector(19 downto 0);
signal reg_crc20           : STD_LOGIC_vector(19 downto 0) := x"00000";
 
signal m_comb_error_i      :  std_logic;
signal pipe_lock           :  std_logic;
signal valid_low           :  std_logic;
signal valid_low_1         :  std_logic;
signal valid_low_2         :  std_logic;
signal valid_low_3         :  std_logic;
 
begin
 
 
 
----first pipeline stage-----
--process (aurora_user_clk) begin
process (aurora_user_clk, reset, pkt_len_violation_i, aurora_chan_stat(0), pipe_lock) begin
--Making asynchronous reset because aurora_user_clk stops during reset 
     if (reset = '1') or (pkt_len_violation_i = '1') or (aurora_chan_stat(0) = '0') or (pipe_lock = '1') then   
--     if (reset = '1') then --or (pkt_len_violation_i = '1') then  --2021_05_01 EF removing pkt_len_violation_i     
         axis_tvalid_1 <= '0'; 
         axis_tlast_1  <= '0'; 
--         axis_tdata_1  <= (others => '0');  --no need to reset data 
         first_cyc_1   <= '0';
   
    elsif rising_edge (aurora_user_clk) then
     axis_tdata_1  <= s_axis_tdata; 
     comb_error_1  <= comb_error;
--     if (reset = '1') or (pkt_len_violation_i = '1') then    
--         axis_tvalid_1 <= '0'; 
--         axis_tlast_1  <= '0'; 
--         first_cyc_1   <= '0';   
--     else 
        axis_tvalid_1 <= s_axis_tvalid; 
        axis_tlast_1  <= s_axis_tlast; 
--        axis_tdata_1  <= s_axis_tdata; 
        first_cyc_1   <= s_first_cyc;
        
--     end if; 
   end if;   
end process; 
 
 
----second pipeline stage-----
--process (aurora_user_clk) begin
process (aurora_user_clk, reset, pkt_len_violation_i, aurora_chan_stat(0)) begin
--Making asynchronous reset because aurora_user_clk stops during reset
    if (reset = '1')or (pkt_len_violation_i = '1') or (aurora_chan_stat(0) = '0') then 
--       if (reset = '1') then --or (pkt_len_violation_i = '1') then  --2021_05_01 EF removing pkt_len_violation_i        
        axis_tvalid_2 <= '0'; 
        axis_tlast_2  <= '0'; 
        first_cyc_2   <= '0';
 
    elsif rising_edge (aurora_user_clk) then
       axis_tdata_2  <= axis_tdata_1; 
       comb_error_2  <= comb_error_1;
 --      if (reset = '1')or (pkt_len_violation_i = '1') then        
 --       axis_tvalid_2 <= '0'; 
 --       axis_tlast_2  <= '0'; 
--first_cyc_2   <= '0'; 
--       else
        axis_tvalid_2 <= axis_tvalid_1; 
        axis_tlast_2  <= axis_tlast_1; 
 --       axis_tdata_2  <= axis_tdata_1; 
        first_cyc_2   <= first_cyc_1;
--       end if;
     end if; 
end process; 
 
----third pipeline stage-----
--process (aurora_user_clk) begin
process (aurora_user_clk, reset, pkt_len_violation_i, aurora_chan_stat(0)) begin
--Making asynchronous reset because aurora_user_clk stops during reset
    if (reset = '1') or (pkt_len_violation_i = '1') or (aurora_chan_stat(0) = '0') then
--      if (reset = '1') then --or (pkt_len_violation_i = '1') then  --2021_05_01 EF removing pkt_len_violation_i 
        axis_tvalid_3 <= '0'; 
        axis_tlast_3  <= '0'; 
        first_cyc_3   <= '0';
        tval_tob_3   <= '0';
        tval_calo_3   <= '0';
    elsif rising_edge (aurora_user_clk) then
      axis_tdata_3  <= axis_tdata_2;
      comb_error_3  <= comb_error_2;
 --     if (reset = '1') or (pkt_len_violation_i = '1') then
 --       axis_tvalid_3 <= '0'; 
 --       axis_tlast_3  <= '0'; 
 --       first_cyc_3   <= '0';
 --       tval_tob_3   <= '0';
 --       tval_calo_3   <= '0';
 --     else
        axis_tvalid_3 <= axis_tvalid_2; 
        axis_tlast_3  <= axis_tlast_2; 
--        axis_tdata_3  <= axis_tdata_2; 
        first_cyc_3   <= first_cyc_2;
        
        tval_tob_3    <= tval_tob;
        tval_calo_3   <= tval_calo; 
     end if;
--   end if;   
end process; 
 
 
----rescue trailer insertion stage 
--process (aurora_user_clk) begin
--    if rising_edge (aurora_user_clk) then
--      if (reset = '1') then
--        axis_tvalid_4 <= '0'; 
--        axis_tlast_4  <= '0'; 
--        first_cyc_4   <= '0';
--        tval_tob_4   <= '0';
--        tval_calo_4   <= '0';
-- --        m_axis_tdata_i  <= (others => '0'); 
--      else
--        axis_tvalid_4 <= axis_tvalid_3; 
--        axis_tlast_4  <= axis_tlast_3;         
--        first_cyc_4   <= first_cyc_3;
--        tval_tob_4    <= tval_tob_3;
--        tval_calo_4   <= tval_calo_3 and not crc_error_3;
--        crc_error_4   <= crc_error_3 and first_cyc_3;       
--        if (terminate_pkt = '1') then
--           axis_tdata_4  <= trailer_value;
--           axis_tlast_4  <= '1';
--        else  
--           axis_tdata_4  <= axis_tdata_3;
--           axis_tlast_4  <= axis_tlast_3;
--        end if;   
--     end if;
--   end if;   
--end process; 
 
----rescue trailer insertion stage 
-->! Note that if there is a crc error, then TVAL_Calo is cleared and TVAL_TOB is set.   
-->! This is because all packets with header crc errors must be routed through the TOB fifo for error processing.
process (aurora_user_clk) begin
    if rising_edge (aurora_user_clk) then
      crc_error_4   <= crc_error_3 and first_cyc_3;
      if (reset = '1') then
        first_cyc_4   <= '0';
        tval_tob_4    <= '0';
        tval_calo_4   <= '0';      
      else         
        first_cyc_4   <= first_cyc_3;
        tval_tob_4    <= tval_tob_3 or (crc_error_3 and first_cyc_3);
        tval_calo_4   <= tval_calo_3 and not crc_error_3;   
     end if;
   end if;   
end process; 
 
process (aurora_user_clk) begin
    if rising_edge (aurora_user_clk) then
      if (reset = '1') then
         axis_tvalid_4 <= '0'; 
         axis_tlast_4  <= '0'; 
         axis_tdata_4  <= axis_tdata_3;
         comb_error_4  <= comb_error_3;
      elsif (terminate_pkt = '1') then
        axis_tdata_4  <= trailer_value;
        axis_tlast_4  <= '1'; 
        axis_tvalid_4 <= '1'; 
      else   
        axis_tvalid_4 <= axis_tvalid_3; 
        axis_tlast_4  <= axis_tlast_3; 
        axis_tdata_4  <= axis_tdata_3;
        comb_error_4  <= comb_error_3;
        
      end if;  
    end if;
end process;    
 
 
trailer_value <= channel_num & "0000" & max_packet_length & x"5a5a5" & x"A" & '0' & "0101100";
--                   12          4            16               20       4      1         7
--trailer_value <= channel_num & "0000" & max_packet_length & reg_crc20 & x"A" & '0' & "0101100";
--                   12          4            16               20        4      1         7
 
----fifth pipeline stage-----
process (aurora_user_clk) begin
    if rising_edge (aurora_user_clk) then
      m_axis_tdata_i  <= axis_tdata_4;
      m_comb_error_i  <= comb_error_4; 
      if (reset = '1') then
        m_axis_tvalid_i <= '0'; 
        m_axis_tlast_i  <= '0'; 
        m_first_cyc_i   <= '0';
         m_tval_tob_i   <= '0';
         m_tval_calo_i   <= '0';
         crc_error_i     <= '0'; 
--        m_axis_tdata_i  <= (others => '0'); 
      else
        m_axis_tvalid_i <= axis_tvalid_4; 
        m_axis_tlast_i  <= axis_tlast_4; 
--        m_axis_tdata_i  <= axis_tdata_4; 
        m_first_cyc_i   <= first_cyc_4;
        m_tval_tob_i    <= tval_tob_4;
        m_tval_calo_i   <= tval_calo_4;
        crc_error_i     <= crc_error_4;     
        
     end if;
   end if;   
end process;    
   
m_axis_tvalid <= m_axis_tvalid_i; 
m_axis_tlast  <= m_axis_tlast_i; 
m_axis_tdata  <= m_axis_tdata_i;       
m_first_cyc    <= m_first_cyc_i;
m_tval_tob     <= m_tval_tob_i;
m_tval_calo    <= m_tval_calo_i; 
m_comb_error   <=  m_comb_error_i;
 
   
process (aurora_user_clk) begin
    if rising_edge (aurora_user_clk) then
       if (reset = '1') then
          tvalid_prev <= '0';
       else   
          tvalid_prev <= (not s_axis_tvalid) or (s_axis_tlast and s_axis_tvalid);
       end if;
    end if;    
 end process;
 
 process(aurora_user_clk, terminate_pkt) begin
     if (terminate_pkt = '1') then
         in_progress <= '0';
     elsif rising_edge (aurora_user_clk) then
        if (reset = '1') or (s_axis_tlast = '1')  then
           in_progress <= '0';
        elsif  (s_first_cyc = '1') and (s_axis_tlast = '0') then  
           in_progress <= '1';
        else 
           in_progress <= in_progress;
        end if;
     end if;    
 end process;
 
--s_first_cyc <= s_axis_tvalid and tvalid_prev and not s_axis_tlast;
s_first_cyc <= s_axis_tvalid and tvalid_prev and not s_axis_tlast and not in_progress;
 
process (aurora_user_clk) begin
    if rising_edge (aurora_user_clk) then
       if (reset = '1') then
             header_crc <= (others => '0');
       else
             header_crc <= axis_tdata_2(28 downto 20);
       end if;
    end if;    
 end process;
--header_crc <= axis_tdata_2(28 downto 20); 
 
crc_input_low <= axis_tdata_1(63 downto 32); 
crc_input_flip <= axis_tdata_1(31 downto 29) & "000000000" & axis_tdata_1(19 downto 0) & axis_tdata_1(63 downto 32);
 
crc_gen : CRC
  generic map (
     Nbits      => 64,
     CRC_Width  =>  9,
--     G_Poly: Std_Logic_Vector :=x"17d";
     --G_Poly: Std_Logic_Vector := "101111101";
     G_Poly      => "011111011",
     G_InitVal   => "111111111"
     )
  port map (
    CRC   => generated_CRC,
    Calc  => first_cyc_1,
    Clk   => aurora_user_clk,
    DIn   => crc_input_flip, 
    Reset => first_cyc_1 
   );
   
crc_error_3 <= '1' when generated_CRC /= header_crc else '0';
 
crc_error <= crc_error_i;
 
---------------------------------IN PROGRESS----------------------------------------------------
--CRC20 is being removed from the input pipe.  It was placed here in order to build the Corrrective Trailer if needed, 
--However, I've realised that there is no time to insert the corrective header without the risk of losing an incoming data word.
--The Aurora input can not be held back for any cycles.  
--crc20_gen : CRC
-- generic map (
--     Nbits     => 64,
--     CRC_Width => 20,
-- --    G_Poly    => x"c1acf",
--     G_Poly    => x"8349f",
--     G_InitVal => x"fffff"
--     )
--  port map (
--    CRC   => generated_CRC20,
--    Calc  => calc_crc20,
--    Clk   => aurora_user_clk,
--    DIn(31 downto 0)   => axis_tdata_1(63 downto 32), 
--    DIn(63 downto 32)   => axis_tdata_1(31 downto 0),
 ---   Reset => first_cyc_1 
--   );
--
--calc_crc20 <= not first_cyc_1 and axis_tvalid_1;
--
--process (aurora_user_clk) begin
--    if rising_edge (aurora_user_clk) then
--         if reset = '1' then 
--              reg_crc20<= x"00000";
--         elsif axis_tlast_3 = '1' then 
--              reg_crc20 <=  generated_CRC20;
--         else   
--              reg_crc20 <= reg_crc20;
--         end if; 
--     end if;
--end process;         
---------------------------------------------------------------------------------------
 
--stream ID decoding 
--tval_tob <= first_cyc_2 and axis_tdata_2(0) and not axis_tdata_2(1);
--tval_calo <= first_cyc_2 and axis_tdata_2(6);-- and not s_crc_error;
--updated streamid definition 25-Nov-19
tval_tob <= first_cyc_2 and not axis_tdata_2(7);
tval_calo <= first_cyc_2 and axis_tdata_2(7);-- and not s_crc_error;
 
--packet length counter
process (aurora_user_clk, pkt_len_violation_i) begin
    if pkt_len_violation_i = '1' then                     -- async (p)reset -> put 'reset in sensitivity list
          pkt_count <= (others => '0');  
    elsif rising_edge (aurora_user_clk) then
       if (reset = '1') or (s_axis_tlast = '1') or (pipe_lock = '1') then -- or (terminate_pkt = '1') then
          pkt_count <= (others => '0');
       elsif (s_axis_tvalid  = '1') then    
          pkt_count <= (pkt_count + 1);
       else 
          pkt_count <= pkt_count;   
       end if;
    end if;    
 end process;
 
 
--2021_04_30  EF disabling terminate packet function due to problems with aurora_user_clk stopping 
--terminate_pkt <= '0'; 
-- process (aurora_user_clk) begin
--    if rising_edge (aurora_user_clk) then
--       if (reset = '1') or (terminate_pkt = '1') then
--          terminate_pkt <= '0';
--       elsif (pkt_count = max_packet_length) then    
--          terminate_pkt <= '1'; 
--       end if;
--    end if;    
-- end process;
--replacing above with a flag set function
 
--2021_05_05 EF restoring terminate_pkt function but clocked with pp_clock instead of aurora_user_clk
--and triggering on pkt_count >=
 
 process (pp_clock) begin
 --   if rising_edge (aurora_user_clk) then
    if rising_edge (pp_clock) then
       if (reset = '1') or (terminate_pkt_1 = '1') then
          terminate_pkt_1 <= '0';
       elsif (pkt_count >= max_packet_length) and (pkt_len_violation_i = '0') then    
          terminate_pkt_1 <= '1'; 
       end if;
    end if;    
 end process;
 
 process (pp_clock) begin
 --   if rising_edge (aurora_user_clk) then
    if rising_edge (pp_clock) then
        terminate_pkt_2 <= terminate_pkt_1;      
    end if;    
 end process;
 
 terminate_pkt <= terminate_pkt_1 or terminate_pkt_2;
--replacing above with a flag set function 
 
 
 
process (aurora_user_clk) begin
    if rising_edge (aurora_user_clk) then
       if (reset = '1') or (terminate_pkt_flag = '1') then
          terminate_pkt_flag <= '0';
       elsif (pkt_count = max_packet_length) then    
          terminate_pkt_flag <= '1'; 
       end if;
    end if;    
 end process;
 
 
--pkt_len_violation <= terminate_pkt;
--add pulse stretcher onto terminate_pkt to make lkt_len_violation 
 
pulse_stretcher : pulse_stretch 
    generic map (
                COUNTER_WIDTH => 4       
            )    
    Port map ( 
--          clock => aurora_user_clk,   --ef changing this to pp_clock because aurora_user_clk was stopping and causing continuous assertion of pkt_len_violation_i  
          clock => pp_clock,
          reset => reset,
          pulse_in =>  terminate_pkt,
--          pulse_in =>  terminate_pkt_flag,
          pulse_out =>  pkt_len_violation_i                 
      );
 
pkt_len_violation <= pkt_len_violation_i;
 
 
--pipe lock is to keep the pipe clean following a max packet length error.  Pipe Lock is cleared when tvalid is brought low 
--indicating that the FEX has regained control or that the Aurora link has been reset.  
 
--because jfex s_axis_tvali is always low every second cycle, it's necessary to detect multiple cycles where it is low in 
-- order to determine if the FEX has really stopped sending 
 
--This scheme doesn't sample tlast, so it could be fooled if the FEX sends a never-ending packet using bursts of tvalid and no tlast. 
 
process (aurora_user_clk, pkt_len_violation_i) begin
    if pkt_len_violation_i = '1' then                     
          valid_low_1 <= '0';  
          valid_low_2 <= '0';
          valid_low_3 <= '0';
    elsif rising_edge (aurora_user_clk) then
          valid_low_1 <=  not s_axis_tvalid;
          valid_low_2 <=  valid_low_1; 
          valid_low_3 <=  valid_low_2; 
    end if; 
 end process;
 
 valid_low <= valid_low_1  and valid_low_2 and valid_low_3;
           
 
 
process (aurora_user_clk, pkt_len_violation_i) begin
    if pkt_len_violation_i = '1' then                     
          pipe_lock <= '1';  
    elsif rising_edge (aurora_user_clk) then
       if (valid_low = '1') then -- 
          pipe_lock <= '0';
       else
          pipe_lock <= pipe_lock;   
       end if;
    end if;    
 end process;
 
end RTL;