RTL Architecture Reference

Processes
PROCESS_6	( aurora_user_clk , reset , pkt_len_violation_i , aurora_chan_stat( 0 ) , pipe_lock )
PROCESS_7	( aurora_user_clk , reset , pkt_len_violation_i , aurora_chan_stat( 0 ) )
PROCESS_8	( aurora_user_clk , reset , pkt_len_violation_i , aurora_chan_stat( 0 ) )
PROCESS_9	( aurora_user_clk )
PROCESS_10	( aurora_user_clk )
PROCESS_11	( aurora_user_clk )
PROCESS_12	( aurora_user_clk )
PROCESS_13	( aurora_user_clk , terminate_pkt )
PROCESS_14	( aurora_user_clk )
PROCESS_15	( aurora_user_clk , pkt_len_violation_i )
PROCESS_16	( pp_clock )
PROCESS_17	( pp_clock )
PROCESS_18	( aurora_user_clk )
PROCESS_19	( aurora_user_clk , pkt_len_violation_i )
PROCESS_20	( aurora_user_clk , pkt_len_violation_i )

Components
CRC	<Entity CRC>
pulse_stretch	<Entity pulse_stretch>

Signals
axis_tvalid_1	STD_LOGIC := ' 0 '
axis_tlast_1	STD_LOGIC := ' 0 '
axis_tdata_1	STD_LOGIC_VECTOR ( 63 downto 0 )
first_cyc_1	STD_LOGIC := ' 0 '
comb_error_1	STD_LOGIC := ' 0 '
axis_tvalid_2	STD_LOGIC := ' 0 '
axis_tlast_2	STD_LOGIC := ' 0 '
axis_tdata_2	STD_LOGIC_VECTOR ( 63 downto 0 )
first_cyc_2	STD_LOGIC := ' 0 '
comb_error_2	STD_LOGIC := ' 0 '
axis_tvalid_3	STD_LOGIC := ' 0 '
axis_tlast_3	STD_LOGIC := ' 0 '
axis_tdata_3	STD_LOGIC_VECTOR ( 63 downto 0 )
first_cyc_3	STD_LOGIC := ' 0 '
comb_error_3	STD_LOGIC := ' 0 '
tval_tob_3	STD_LOGIC := ' 0 '
tval_calo_3	STD_LOGIC := ' 0 '
axis_tvalid_4	STD_LOGIC := ' 0 '
axis_tlast_4	STD_LOGIC := ' 0 '
axis_tdata_4	STD_LOGIC_VECTOR ( 63 downto 0 )
first_cyc_4	STD_LOGIC := ' 0 '
comb_error_4	STD_LOGIC := ' 0 '
tval_tob_4	STD_LOGIC := ' 0 '
tval_calo_4	STD_LOGIC := ' 0 '
m_axis_tvalid_i	STD_LOGIC := ' 0 '
m_axis_tlast_i	STD_LOGIC := ' 0 '
m_axis_tdata_i	STD_LOGIC_VECTOR ( 63 downto 0 )
m_first_cyc_i	STD_LOGIC := ' 0 '
s_first_cyc	STD_LOGIC
tvalid_prev	STD_LOGIC := ' 0 '
generated_crc	STD_LOGIC_VECTOR ( 8 downto 0 )
header_crc	STD_LOGIC_VECTOR ( 8 downto 0 )
crc_error_i	STD_LOGIC
crc_error_3	STD_LOGIC := ' 0 '
crc_error_4	STD_LOGIC := ' 0 '
crc_input_low	STD_LOGIC_VECTOR ( 31 downto 0 )
crc_input_high	STD_LOGIC_VECTOR ( 31 downto 0 )
crc_input_flip	STD_LOGIC_VECTOR ( 63 downto 0 )
m_tval_tob_i	STD_LOGIC := ' 0 '
tval_tob	STD_LOGIC := ' 0 '
m_tval_calo_i	STD_LOGIC := ' 0 '
tval_calo	STD_LOGIC := ' 0 '
pkt_count	STD_LOGIC_VECTOR ( 15 downto 0 ) := x " 0000 "
trailer_value	STD_LOGIC_VECTOR ( 63 downto 0 )
terminate_pkt	STD_LOGIC := ' 0 '
terminate_pkt_1	STD_LOGIC := ' 0 '
terminate_pkt_2	STD_LOGIC := ' 0 '
terminate_pkt_flag	STD_LOGIC := ' 0 '
pkt_len_violation_i	STD_LOGIC := ' 0 '
in_progress	STD_LOGIC
calc_crc20	STD_LOGIC
generated_crc20	STD_LOGIC_vector ( 19 downto 0 )
reg_crc20	STD_LOGIC_vector ( 19 downto 0 ) := x " 00000 "
m_comb_error_i	std_logic
pipe_lock	std_logic
valid_low	std_logic
valid_low_1	std_logic
valid_low_2	std_logic
valid_low_3	std_logic

Instantiations
crc_gen	CRC <Entity CRC>
pulse_stretcher	pulse_stretch <Entity pulse_stretch>

Detailed Description

Definition at line 64 of file aurora_pipe.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/aurora_pipe.vhd