clock_test_ipbus Entity Reference

Inheritance diagram for clock_test_ipbus:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
STD_LOGIC_UNSIGNED

Generics
COUNTER_WIDTH_40	integer := 8
reset_count	std_logic_vector ( 15 downto 0 ) := x " 03ff "
count_40_term	std_logic_vector ( 7 downto 0 ) := x " 45 "
count_160_term	std_logic_vector ( 7 downto 0 ) := x " 45 "

Ports
clock_40	in	STD_LOGIC
clock_160	in	STD_LOGIC
clock_125	in	STD_LOGIC
reset	in	STD_LOGIC
clock_160_lock	in	STD_LOGIC
clk_40_good	out	std_logic
clk_160_good	out	std_logic
count_40	out	std_logic_vector ( counter_width_40- 1 downto 0 )
count_160	out	std_logic_vector ( counter_width_40- 1 downto 0 )
count_125	out	std_logic_vector ( counter_width_40- 1 downto 0 )

Detailed Description

Definition at line 52 of file clock_test_ipbus.vhd.

---

The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/clock_test_ipbus.vhd