clock_test_ipbus.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.02.2019 13:36:52
-- Design Name: 
-- Module Name: reset_count - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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-->the ROD has three primary clock sources: 
--> 1) The Si chip - takes 40MHz from Hub and produces clean 40MHz inputs to the FPGA and the TI chip 
--> 2) The TI chip - takes 40MHz from the Si chip, and produces the 160MHz and 240MHz MGT reference clocks.  If the Si chip is not working, 
-->    then this device will also fail to produce the correct frequencies 
--> 3) The ethernet PHY chip has a 25MHz oscilator and it produces a 125MHz signal to the FPGA when working properly. If this chip is not working properly
-->    it has been observed to produce 25MHz or even a random frequence like 116MHz.   However, since the results of this checker are intended to 
-->    be read via IPBus, we have to assume that the 125MHz is working correctly.  
-->     Thus there is no explicite 125MHz check  
 
--> The circuit below resets all three counters at the end of each measurement sequence.  
--> The length of the sequence is determined by the "reset_count" generic
--> At the end of each sequence the values of clk_40_count and clk_160_count are checked against a constant value
-->  If the value matches within a range, then the "good" bit is set
-->  If the value does not match within the range, then the "good" bit is cleared. 
 
 
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity clock_test_ipbus is
  generic
(
 COUNTER_WIDTH_40  : integer :=   8;
 reset_count       : std_logic_vector(15 downto 0) := x"03ff";   --count_125 rollover resets the system
 count_40_term     : std_logic_vector(7 downto 0) := x"45";    
 count_160_term    : std_logic_vector(7 downto 0) := x"45"  
 
 --for a shorter test sequence, use the values below 
 --reset_count       : std_logic_vector(15 downto 0) := x"01ff";   --count_125 rollover resets the system
 --count_40_term     : std_logic_vector(7 downto 0) := x"A2";    
 --count_160_term    : std_logic_vector(7 downto 0) := x"A2"  
);    
 
    Port ( 
               clock_40         : in STD_LOGIC;
               clock_160        : in STD_LOGIC;
               clock_125        : in STD_LOGIC;
               reset            : in STD_LOGIC;
               clock_160_lock   : in STD_LOGIC;
               clk_40_good      : out std_logic;
               clk_160_good     : out std_logic;
               count_40         : out std_logic_vector(counter_width_40-1 downto 0);
               count_160        : out std_logic_vector(counter_width_40-1 downto 0);
               count_125        : out std_logic_vector(counter_width_40-1 downto 0)
                
               );
end clock_test_ipbus;
 
architecture RTL of clock_test_ipbus is
 
signal counter_40 :  std_logic_vector(counter_width_40-1 downto 0) := (others => '0');
signal counter_160 :  std_logic_vector(counter_width_40+2-1 downto 0) := (others => '0');
signal counter_125 :  std_logic_vector(counter_width_40+8-1 downto 0) := (others => '0');
signal clk_40_good_i :  std_logic;
signal clk_160_good_i :  std_logic;
signal clk_125_good_i :  std_logic;
signal reset_timer : std_logic_vector(3 downto 0) := (others => '0');
signal timed_reset : std_logic;
signal timed_reset_40 : std_logic;
signal timed_reset_160 : std_logic;
 
begin
process (clock_40) begin 
 
  if rising_edge (clock_40) then 
   if reset = '1' or timed_reset_40 = '1' then --counter_125 = reset_count then 
        counter_40 <= (others => '0');
      else      
       counter_40 <= counter_40+1; 
      end if;   
 end if; 
end process;  
 
process (clock_160) begin 
  if rising_edge (clock_160) then 
    if reset = '1' or clock_160_lock = '0' or timed_reset_160 = '1' then --counter_125 = reset_count then 
        counter_160 <= (others => '0');
     else      
        counter_160 <= counter_160 +1;  
     end if;   
  end if; 
end process;
 
process (clock_125) begin 
  if rising_edge (clock_125) then 
      if (reset = '1') or timed_reset = '1'  then 
        counter_125 <= (others => '0');
      else    
        counter_125 <= counter_125 +1;
      end if;    
  end if; 
end process;
 
 
 
count_40 <= counter_40;
 
count_160 <= counter_160(counter_width_40+2-1 downto 2);
 
count_125 <= counter_125(counter_width_40+2-1 downto 2);
 
process (clock_125) begin 
  if rising_edge (clock_125) then 
     if reset = '1' or counter_125 = reset_count then 
         reset_timer <= x"f"; 
     elsif reset_timer /= x"0" then 
         reset_timer <= reset_timer -1;
     else      
        reset_timer <= reset_timer;
     end if; 
  end if;   
end process;        
 
--timed_reset <= '1' when reset_timer /= x"0" else '0';
timed_reset <= reset_timer(3) or reset_timer(2) or reset_timer(1) or reset_timer(0);
-- reset the timers using the 125MHz clock rollover 
 
process (clock_40) begin
 if rising_edge (clock_40) then  
     timed_reset_40 <= timed_reset;
 end if;
end process;  
 
process (clock_160) begin
 if rising_edge (clock_160) then  
     timed_reset_160 <= timed_reset;
 end if;
end process;
 
 
 
--check clk_40 using clk_125 
--the clk_40 timer should reach a specific value +/- 4 just before the 125 counter rolls over 
--after the clk_40 counter value is checked, all of the counters are reset to start the nect test sequence.
 
process (clock_125) begin
 if rising_edge (clock_125) then  
     if reset = '1' then 
          clk_40_good_i <= '0';  
     elsif (counter_125 = reset_count - 4) then 
           if (counter_40 >= (count_40_term -4)) and  (counter_40 <= (count_40_term +4)) then 
              clk_40_good_i <= '1';
           elsif (counter_40 <= (count_40_term -4)) or  (counter_40 >= (count_40_term +4)) then 
              clk_40_good_i <= '0';
           else 
              clk_40_good_i <= clk_40_good_i;   
           end if; 
     else 
        clk_40_good_i <= clk_40_good_i;           
     end if; 
 end if;   
end process;      
 
--check clk_160 using clk_125 
--the clk_160 timer should reach a specific value +/- 4 just before the 125 counter rolls over 
--after the clk_160 counter value is checked, all of the counters are reset to start the nect test sequence.
 
process (clock_125) begin
 if rising_edge (clock_125) then  
     if reset = '1' then 
          clk_160_good_i <= '0';  
     elsif (counter_125 = reset_count - 4) then 
           if (counter_160(9 downto 2) >= (count_160_term -4)) and  (counter_160(9 downto 2) <= (count_160_term +4)) then 
              clk_160_good_i <= '1';
           elsif (counter_160(9 downto 2) <= (count_160_term -4)) or  (counter_160(9 downto 2) >= (count_160_term +4)) then 
              clk_160_good_i <= '0';
           else 
              clk_160_good_i <= clk_160_good_i;   
           end if; 
     else 
        clk_160_good_i <= clk_160_good_i;           
     end if; 
 end if;   
end process;      
 
clk_40_good <= clk_40_good_i;
clk_160_good <= clk_160_good_i;
 
 
 
 
--> clock Status Register 
--> (15 downto 8)  clk_160_count 
--> (23 downto 16)  clk_40_count
--> (31 downto 24)  clk125_count 
-->  (0) clock_160_lock
-->  (1) clk_160_good 
-->  (2) clk_40_good
 
 
end RTL;