RTL Architecture Reference

Processes
PROCESS_101	( clock_40 )
PROCESS_102	( clock_160 )
PROCESS_103	( clock_125 )
PROCESS_104	( clock_125 )
PROCESS_105	( clock_40 )
PROCESS_106	( clock_160 )
PROCESS_107	( clock_125 )
PROCESS_108	( clock_125 )

Signals
counter_40	std_logic_vector ( counter_width_40- 1 downto 0 ) := ( others = > ' 0 ' )
counter_160	std_logic_vector ( counter_width_40+ 2 - 1 downto 0 ) := ( others = > ' 0 ' )
counter_125	std_logic_vector ( counter_width_40+ 8 - 1 downto 0 ) := ( others = > ' 0 ' )
clk_40_good_i	std_logic
clk_160_good_i	std_logic
clk_125_good_i	std_logic
reset_timer	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
timed_reset	std_logic
timed_reset_40	std_logic
timed_reset_160	std_logic

Detailed Description

Definition at line 81 of file clock_test_ipbus.vhd.

---

The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/clock_test_ipbus.vhd