ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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input_capture Entity Reference
Inheritance diagram for input_capture:
packet_crc CRC osum_crc9d32 input_capture_regs tob_proc_regs tob_processor packet_processor rod_top top_rod_efex top_rod_jfex

Entities

RTL  architecture
 

Libraries

IEEE 

Use Clauses

STD_LOGIC_1164 
std_logic_unsigned 
NUMERIC_STD 

Generics

packet_version  std_logic_vector ( 2 downto 0 ) := " 001 "
addr_width  integer := 4
sim  integer := 0
debug  integer := 1

Ports

pp_clock   in   std_logic
ipb_rst   in   std_logic
input_capture_control   in   std_logic_vector ( 31 downto 0 )
s_tvalid   in   std_logic
s_tlast   in   std_logic
s_tdata   in   std_logic_vector ( 63 downto 0 )
poll_chan   in   std_logic
current_chan   in   std_logic_vector ( 4 downto 0 )
selected_chan   in   std_logic_vector ( 4 downto 0 )
timeout_err   in   std_logic
pkt_count   out   std_logic_vector ( 31 downto 0 )
input_header   out   std_logic_vector ( 63 downto 0 )
input_trailer   out   std_logic_vector ( 63 downto 0 )
capture_status   out   std_logic_vector ( 31 downto 0 )
header_crc9_error   out   std_logic
payload_crc20_error   out   std_logic
length_error   out   std_logic
spy_we   out   std_logic
spy_addr   out   std_logic_vector ( addr_width- 1 downto 0 )

Detailed Description

Definition at line 37 of file input_capture.vhd.


The documentation for this class was generated from the following file: