input_capture.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 30.03.2022 17:58:23
-- Design Name: 
-- Module Name: input_capture - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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--capture a 64-bit header when 
--  (ARMED = '1') AND (C=current_chan = selected_chan) 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity input_capture is
   generic (
        packet_version   : std_logic_vector(2 downto 0)    := "001";
        addr_width       : integer    := 4; 
        sim              : integer    := 0; 
        debug            : integer    := 1
        ); 
  Port ( 
          pp_clock                  : in std_logic;
          ipb_rst                   : in std_logic;
          input_capture_control     : in std_logic_vector(31 downto 0);
          s_tvalid                  : in std_logic;
          s_tlast                   : in std_logic;
          s_tdata                   : in std_logic_vector(63 downto 0);
          poll_chan                 : in std_logic;
          
          current_chan              : in std_logic_vector(4 downto 0);
          selected_chan             : in std_logic_vector(4 downto 0);
          
          timeout_err               : in std_logic;
          
          pkt_count                 : out std_logic_vector(31 downto 0);
      
          input_header              : out std_logic_vector(63 downto 0);
          input_trailer             : out std_logic_vector(63 downto 0);
          capture_status            : out std_logic_vector(31 downto 0);
          header_crc9_error         : out std_logic;
          payload_crc20_error       : out std_logic;
          length_error              : out std_logic;
          
          spy_we                    : out std_logic;
          spy_addr                  : out std_logic_vector(addr_width-1 downto 0)
 
          
        );
end input_capture;
 
architecture RTL of input_capture is
 
component packet_crc is
  generic (
    fex_check             : integer := 0;
    crc20_G_Poly          : std_logic_vector(19 downto 0) := x"8349f"   --old poly
    );
  Port ( 
  clock         : in    std_logic;
  reset         : in    std_logic;
  s_tvalid      : in    std_logic;
  s_tlast       : in    std_logic;
  s_tdata       : in    std_logic_vector(63 downto 0);
  header_error  : out   std_logic;
  payload_error : out   std_logic;
  length_error  : out   std_logic
  );
end component;
 
 
 
signal clear                   : std_logic;
signal clear_s                 : std_logic;
signal clear_s_del             : std_logic;
signal armed                   : std_logic;
signal armed_s                 : std_logic;
signal armed_s_del             : std_logic;
signal armed_pulse             : std_logic;
signal armed_stat              : std_logic;
signal triggered               : std_logic;
signal capture                 : std_logic; 
signal tvalid_prev             : std_logic;
signal l_header_marker         : std_logic;     --replaces m_header_marker input 
 
signal arm_for_timeout         : std_logic;
signal armed_timeout_stat      : std_logic;
signal armed_for_timeout_del   : std_logic;
signal armed_for_timeout_pulse : std_logic;
 
 
signal m_header_marker_2       : std_logic; 
signal header_0                : std_logic_vector(63 downto 0);
signal header_0_i              : std_logic_vector(31 downto 0);
signal header_2                : std_logic_vector(31 downto 0);
signal trailer                 : std_logic_vector(63 downto 0);
 
signal incomp_pkt              : std_logic;
--signal capture_status          : std_logic_vector(31 downto 0);
 
signal pkt_count_i             : std_logic_vector(31 downto 0);
 
signal tvalid_dup              : std_logic;
signal poll_chan_del           : std_logic;
signal poll_chan_del2           : std_logic;
signal crc_reset               : std_logic;
 
signal header_crc9_error_i     : std_logic;
signal payload_crc20_error_i   : std_logic;
signal length_error_i          : std_logic;
 
signal spy_addr_i              : std_logic_vector(addr_width-1 downto 0);
signal spy_addr_max            : std_logic_vector(addr_width-1 downto 0);
 
begin
spy_addr_max <= (others => '1');
 
-----capture mech -------------------
--requires following six IPBus registers: 
 
--input_capture_channel_select (read/write) 
--   drives the selected_channel(4 downto 0)
 
--input_capture_control  (pulse) 
--     input_capture_control(0) = arm 
--     input_capture_control(1) = clear
 
--Input_Header_0 (read only) 
--     first 32-bit header word     (input_header(31 downto 0) 
--Input_Header_1 (read only) 
--     second 32-bit header word    (input_header(63 downto 32))
 
--Input_Trailer_0 (read only) 
--     first 32-bit trailer word     (input_trailer(31 downto 0)) 
--Input_Trailer_1 (read only) 
--     second 32-bit trailer word    (input_trailer(63 downto 32)) 
 
 
-----------------------------------------------------------------------------
 
-------sample the pulse reg in the pp_clock domain ------
--armed_s samples the pulse bit running on ipb_clk
--armed_s_del sample armed_s synchronously on pp_clock
--armed_stat is the user's status flag indicating the mech is armed, but not triggered
 
--clear <= pkt_capture_control(1);
 
--clear pulse happens on trailing edge of ipbus pulse 
process(pp_clock) begin
  if rising_edge (pp_clock) then
     clear_s <= input_capture_control(1);
     clear_s_del <= clear_s; 
  end if;   
end process;
 
clear <= clear_s_del and not clear_s;
 
 
process(pp_clock) begin
  if rising_edge (pp_clock) then
     armed_s <= input_capture_control(0);
     armed_s_del <= armed_s; 
  end if;   
end process;
 
armed_pulse <= armed_s_del and not armed_s;
 
process(pp_clock) begin
  if rising_edge (pp_clock) then
     if (ipb_rst = '1') or (capture = '1') or (clear = '1') then
       armed_stat <= '0';
     elsif (armed_pulse = '1') then 
       armed_stat <= '1';         
     else 
       armed_stat <= armed_stat;     
     end if;  
  end if;
end process;
 
 
--- capture after timeout ---
process(pp_clock) begin
  if rising_edge (pp_clock) then
     if (ipb_rst = '1') or (capture = '1') or (clear = '1') then
        arm_for_timeout <= '0';
     elsif (input_capture_control(2) = '1') then 
        arm_for_timeout <= '1';
     else 
        arm_for_timeout <= arm_for_timeout; 
     end if;
  end if;
end process;
 
process(pp_clock) begin
  if rising_edge (pp_clock) then            
     armed_for_timeout_del <= arm_for_timeout;
   end if;   
end process;    
 
--process(pp_clock) begin
--  if rising_edge (pp_clock) then
--     arm_for_timeout <= input_capture_control(2);
--     armed_for_timeout_del <= arm_for_timeout;
--  end if;   
--end process;
 
--armed_for_timeout_pulse <= armed_for_timeout_del and not arm_for_timeout;
armed_for_timeout_pulse <= arm_for_timeout and not armed_for_timeout_del;
 
process(pp_clock) begin
  if rising_edge (pp_clock) then
     if (ipb_rst = '1') or (capture = '1') or (clear = '1') then
       armed_timeout_stat <= '0';
     elsif (arm_for_timeout = '1') and ((timeout_err = '1') and (current_chan = selected_chan)) then 
       armed_timeout_stat <= '1';         
     else 
       armed_timeout_stat <= armed_timeout_stat;     
     end if;  
  end if;
end process;
 
----------------------------------
 
--The header marker coming from the TOB processor is not currently reliable, so a stand alone version is created here 
process (pp_clock) begin
    if rising_edge (pp_clock) then
       if (ipb_rst = '1') or (clear = '1') then
          tvalid_prev <= '0';
       else
          tvalid_prev <= (not s_tvalid) or (s_tlast and s_tvalid);
       end if;
    end if;
 end process;
 
l_header_marker <= s_tvalid and tvalid_prev; 
 
 
 
 
-- Capture - active during the event being captured and then cleared --  
process(pp_clock) begin
  if rising_edge (pp_clock) then
      if (ipb_rst = '1') or (clear = '1') then 
          capture <= '0';
--      elsif (armed_stat = '1') and (l_header_marker = '1') and (s_tvalid = '1') and (current_chan = selected_chan) then 
      elsif ((armed_stat = '1') or (armed_timeout_stat = '1')) and (l_header_marker = '1') and (s_tvalid = '1') and (current_chan = selected_chan) then 
          capture <= '1'; 
      elsif (capture = '1') and (s_tlast = '1') then 
          capture <= '0';
      else 
          capture <= capture;          
      end if;
   end if;    
end process;          
 
-- triggered - status bit to indicate an event has been captured 
process(pp_clock) begin
   if rising_edge (pp_clock) then
      if (ipb_rst = '1') or (clear = '1') then 
         triggered <= '0';            
      elsif (capture = '1') then 
          triggered <= '1';
      elsif (armed_pulse = '1') or (armed_for_timeout_pulse = '1') then 
          triggered <= '0';
      else 
          triggered <= triggered;                
      end if; 
   end if;    
end process;
 
-- capture the header 
process(pp_clock) begin
   if rising_edge (pp_clock) then
      if  (clear = '1') then 
             header_0 <= (others => '0');
--      elsif (armed_stat = '1' ) and (l_header_marker = '1') then 
      elsif ((armed_stat = '1' ) or (armed_timeout_stat = '1')) and (l_header_marker = '1') and (s_tvalid = '1') and (current_chan = selected_chan) then 
             header_0 <= s_tdata; 
      else 
          header_0 <= header_0;    
      end if; 
   end if;
end process;           
          
 
 
--capture trailer 
process(pp_clock) begin
   if rising_edge (pp_clock) then
      if (clear = '1') then 
          trailer <= (others => '0');
      elsif  (capture = '1' ) and (s_tlast = '1') then 
          trailer <= s_tdata;
      else 
          trailer <= trailer;     
      end if; 
   end if;
end process;
 
 
--incomp_pkt is active while capture is active:   
incomp_pkt <= capture;
 
 
--capture_status <=  '0' & packet_version & x"000000"  & '0'  & incomp_pkt & triggered  & armed_stat;
 
capture_status(0) <= armed_stat;
capture_status(1) <= triggered;
capture_status(2) <= incomp_pkt;
capture_status(3) <= arm_for_timeout;
capture_status(4) <= header_crc9_error_i;
capture_status(5) <= payload_crc20_error_i;
capture_status(6) <= length_error_i;
capture_status(27 downto 7) <= (others => '0');
capture_status(30 downto 28) <= packet_version;
capture_status(31) <= '0';
 
 
--packet counter  
process(pp_clock) begin
   if rising_edge (pp_clock) then
      if (ipb_rst = '1') or (clear = '1') then 
          pkt_count_i <= (others => '0');
      elsif  (s_tlast = '1') and (s_tvalid = '1') and (current_chan = selected_chan) then 
          pkt_count_i  <= (pkt_count_i + 1);
      else 
          pkt_count_i <= pkt_count_i;     
      end if; 
   end if;
end process;
 
pkt_count <= pkt_count_i;
input_header <= header_0;
input_trailer <= trailer;
 
crc_checker : packet_crc 
 generic map ( 
     fex_check      => 1, 
     crc20_G_Poly   => x"8359f" 
     )
  Port map( 
    clock         =>  pp_clock,
    reset         =>  crc_reset,
    s_tvalid      =>  tvalid_dup,
    s_tlast       =>  s_tlast,
    s_tdata       =>  s_tdata,
    header_error  =>  header_crc9_error_i,
    payload_error =>  payload_crc20_error_i,
    length_error  =>  length_error_i
  );
 
crc_reset <= clear or armed_pulse; 
 
 
header_crc9_error <= header_crc9_error_i;
payload_crc20_error <= payload_crc20_error_i;
length_error <= length_error_i;
 
 
 
---tvalid_dup generation: real tvalid is held avtive after a packet arrives at the head of the queue, 
-- but before the processor does a polling operation to begin reading it.  tvalid_dup is a duplicated tvalid which accounts for 
-- the error before fifo reading (polling)  begins 
 
process (pp_clock) begin
   if rising_edge (pp_clock) then
     poll_chan_del <= poll_chan; 
     poll_chan_del2 <= poll_chan_del;
   end if; 
end process;      
     
 
 
process (pp_clock) begin
   if rising_edge (pp_clock) then
      if (ipb_rst = '1') or (clear = '1') or (s_tlast = '1') then 
          tvalid_dup <= '0';
      elsif  (poll_chan_del = '1') and (s_tvalid = '1') and (current_chan = selected_chan) and (capture = '1')  then 
          tvalid_dup <= '1';
      elsif s_tlast = '1' then 
          tvalid_dup <= '0';  
      else 
          tvalid_dup <= tvalid_dup;     
      end if; 
   end if;
end process;
 
 
 
--Spy RAM controller ---
spy_we <= tvalid_dup; 
 
process (pp_clock) begin
   if rising_edge (pp_clock) then
      if (ipb_rst = '1') or (clear = '1') or (s_tlast = '1') then 
        spy_addr_i <= (others => '0');
      elsif (tvalid_dup = '1') and (spy_addr_i < spy_addr_max) then 
        spy_addr_i <= spy_addr_i + 1;
      else 
        spy_addr_i <= spy_addr_i; 
      end if;
   end if;      
end process; 
 
spy_addr <= spy_addr_i; 
 
 
end RTL;