ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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Components | Instantiations | Processes | Signals
RTL Architecture Reference

Processes

PROCESS_188  ( pp_clock )
PROCESS_189  ( pp_clock )
PROCESS_190  ( pp_clock )
PROCESS_191  ( pp_clock )
PROCESS_192  ( pp_clock )
PROCESS_193  ( pp_clock )
PROCESS_194  ( pp_clock )
PROCESS_195  ( pp_clock )
PROCESS_196  ( pp_clock )
PROCESS_197  ( pp_clock )
PROCESS_198  ( pp_clock )
PROCESS_199  ( pp_clock )
PROCESS_200  ( pp_clock )
PROCESS_201  ( pp_clock )
PROCESS_202  ( pp_clock )

Components

packet_crc  <Entity packet_crc>

Signals

clear  std_logic
clear_s  std_logic
clear_s_del  std_logic
armed  std_logic
armed_s  std_logic
armed_s_del  std_logic
armed_pulse  std_logic
armed_stat  std_logic
triggered  std_logic
capture  std_logic
tvalid_prev  std_logic
l_header_marker  std_logic
arm_for_timeout  std_logic
armed_timeout_stat  std_logic
armed_for_timeout_del  std_logic
armed_for_timeout_pulse  std_logic
m_header_marker_2  std_logic
header_0  std_logic_vector ( 63 downto 0 )
header_0_i  std_logic_vector ( 31 downto 0 )
header_2  std_logic_vector ( 31 downto 0 )
trailer  std_logic_vector ( 63 downto 0 )
incomp_pkt  std_logic
pkt_count_i  std_logic_vector ( 31 downto 0 )
tvalid_dup  std_logic
poll_chan_del  std_logic
poll_chan_del2  std_logic
crc_reset  std_logic
header_crc9_error_i  std_logic
payload_crc20_error_i  std_logic
length_error_i  std_logic
spy_addr_i  std_logic_vector ( addr_width- 1 downto 0 )
spy_addr_max  std_logic_vector ( addr_width- 1 downto 0 )

Instantiations

crc_checker  packet_crc <Entity packet_crc>

Detailed Description

Definition at line 74 of file input_capture.vhd.


The documentation for this class was generated from the following file: