input_capture_regs Entity Reference

Inheritance diagram for input_capture_regs:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
std_logic_unsigned
NUMERIC_STD
ipbus
ipbus_decode_L1CaloHubRodInputCaptureRegisters

Generics
packet_version	std_logic_vector ( 2 downto 0 ) := " 001 "
addr_width_64	integer := 4
sim	integer := 0
debug	integer := 1

Ports
ipb_clk	in	std_logic
ipb_rst	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
pp_clock	in	std_logic
current_chan	in	STD_LOGIC_VECTOR ( 4 downto 0 )
s_tdata	in	STD_LOGIC_VECTOR ( 63 downto 0 )
s_tvalid	in	std_logic
s_tlast	in	std_logic
s_header_mark	in	std_logic
poll_chan	in	std_logic
timeout_err	in	std_logic

Detailed Description

The Packet Capture Registers are used during debug to capture Headers and Trailers of a packet The user Arm's the mechanism by setting the "arm" bit in the control register.
the capture will begin on the first header which arrives after the mechanism is armed.
After setting the arm control bit, the user should check the "triggered" bit in the status register when triggered is set, then a packet has been captured.
This mechanism can provide simple snapshots of passing packets so that the user can see if they make sense.

Definition at line 18 of file input_capture_regs.vhd.

---

The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/input_capture_regs.vhd