RTL Architecture Reference

Components
input_capture	<Entity input_capture>
ipbus_dpram

Signals
version	std_logic_vector ( 3 downto 0 )
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
capture_control_reg_rst	std_logic
capture_control_reg_stb	std_logic
input_capture_control	std_logic_vector ( 31 downto 0 )
clear	std_logic
clear_s	std_logic
clear_s_del	std_logic
armed	std_logic
armed_s	std_logic
armed_s_del	std_logic
armed_pulse	std_logic
armed_stat	std_logic
triggered	std_logic
capture	std_logic
tvalid_prev	std_logic
l_header_marker	std_logic
capture_status	std_logic_vector ( 31 downto 0 )
pkt_count	std_logic_vector ( 31 downto 0 )
selected_chan	std_logic_vector ( 31 downto 0 )
input_header	std_logic_vector ( 63 downto 0 )
input_trailer	std_logic_vector ( 63 downto 0 )
header_crc9_error	std_logic
payload_crc20_error	std_logic
length_error	std_logic
spy_we	std_logic
spy_addr	std_logic_vector ( addr_width_64- 1 downto 0 )
spy_reset	std_logic
ipb_mux_data	std_logic_vector ( 31 downto 0 )
capture_data_lsw	std_logic_vector ( 31 downto 0 )
capture_data_msw	std_logic_vector ( 31 downto 0 )
ipb_strobe_lsw	std_logic
ipb_strobe_msw	std_logic
ipb_rdata_lsw	std_logic_vector ( 31 downto 0 )
ipb_rdata_msw	std_logic_vector ( 31 downto 0 )
ipb_in_lsw	ipb_wbus
ipb_out_lsw	ipb_rbus
ipb_in_msw	ipb_wbus
ipb_out_msw	ipb_rbus

Instantiations
fabric	ipbus_fabric_sel
input_channel_select_reg	ipbus_reg_v
capture_control_reg	ipbus_reg_v
capture_status_reg	ipbus_syncreg_v
header_0_reg	ipbus_syncreg_v
header_1_reg	ipbus_syncreg_v
trailer_0_reg	ipbus_syncreg_v
trailer_1_reg	ipbus_syncreg_v
pkt_count_reg	ipbus_syncreg_v
capture_lsw	ipbus_dpram
capture_msw	ipbus_dpram
input_capture_mech	input_capture <Entity input_capture>

Detailed Description

Definition at line 42 of file input_capture_regs.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/input_capture_regs.vhd