input_capture_regs.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
--library unisim;
--use unisim.vcomponents.all;
use work.ipbus.all;
use work.ipbus_decode_L1CaloHubRodInputCaptureRegisters.all;
 
 
 
entity input_capture_regs is 
     generic (
        packet_version   : std_logic_vector(2 downto 0)    := "001";
        addr_width_64    : integer    := 4;  --depth of each 32-bit memory
        sim              : integer    := 0; 
        debug            : integer    := 1
        ); 
    Port ( 
 
        ipb_clk            : in std_logic;
        ipb_rst            : in std_logic;
        ipb_in             : in ipb_wbus;
        ipb_out            : out ipb_rbus;  
        pp_clock           : in std_logic;
        current_chan      : in  STD_LOGIC_VECTOR (4 downto 0);
        s_tdata           : in  STD_LOGIC_VECTOR (63 downto 0);
        s_tvalid          : in std_logic;  
        s_tlast           : in std_logic;
        s_header_mark     : in std_logic;
        poll_chan         : in std_logic;
        timeout_err       : in std_logic
        
        );
end input_capture_regs;
architecture RTL of input_capture_regs is   
 
component input_capture
   generic (
        packet_version   : std_logic_vector(2 downto 0)    := "001";
        addr_width       : integer    := (addr_width_64); 
        sim              : integer    := 0; 
        debug            : integer    := 1
        ); 
  Port ( 
          pp_clock                  : in std_logic;
          ipb_rst                   : in std_logic;
          input_capture_control     : in std_logic_vector(31 downto 0);
          s_tvalid                  : in std_logic;
          s_tlast                   : in std_logic;
          s_tdata                   : in std_logic_vector(63 downto 0);
          poll_chan                 : in std_logic;
          
          current_chan              : in std_logic_vector(4 downto 0);
          selected_chan             : in std_logic_vector(4 downto 0);
          
          timeout_err               : in std_logic;
          
          pkt_count                 : out std_logic_vector(31 downto 0);
      
          input_header              : out std_logic_vector(63 downto 0);
          input_trailer             : out std_logic_vector(63 downto 0);
          capture_status            : out std_logic_vector(31 downto 0);
          header_crc9_error         : out std_logic;
          payload_crc20_error       : out std_logic;
          length_error              : out std_logic;
           
          spy_we                    : out std_logic;
          spy_addr                  : out std_logic_vector(addr_width-1 downto 0) 
        );
end component;
 
component ipbus_dpram is
    generic(
        ADDR_WIDTH: positive := addr_width_64;
        DATA_WIDTH: positive := 32
    );
    port(
      
        clk: in std_logic;
        rst: in std_logic;
        ipb_in: in ipb_wbus;
        ipb_out: out ipb_rbus;
        rclk: in std_logic;
        we: in std_logic := '0';
        d: in std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
        q: out std_logic_vector(DATA_WIDTH - 1 downto 0);
        addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0)
    );
    
 
    
end component;
 
 
signal version                : std_logic_vector(3 downto 0);
 
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal capture_control_reg_rst : std_logic;
signal capture_control_reg_stb : std_logic;
signal input_capture_control     : std_logic_vector(31 downto 0);
 
signal clear                   : std_logic;
signal clear_s                 : std_logic;
signal clear_s_del             : std_logic;
signal armed                   : std_logic;
signal armed_s                 : std_logic;
signal armed_s_del             : std_logic;
signal armed_pulse             : std_logic;
signal armed_stat              : std_logic;
signal triggered               : std_logic;
signal capture                 : std_logic; 
signal tvalid_prev             : std_logic;
signal l_header_marker         : std_logic;     --replaces m_header_marker input 
 
--signal m_header_marker_2       : std_logic; 
--signal header_0                : std_logic_vector(63 downto 0);
--signal header_0_i              : std_logic_vector(31 downto 0);
----signal header_2                : std_logic_vector(31 downto 0);
--signal trailer                 : std_logic_vector(63 downto 0);
 
--signal incomp_pkt              : std_logic;
signal capture_status          : std_logic_vector(31 downto 0);
 
signal pkt_count               : std_logic_vector(31 downto 0);
 
signal selected_chan           : std_logic_vector(31 downto 0);
--signal input_capture_control   : std_logic_vector(31 downto 0);
signal input_header            : std_logic_vector(63 downto 0);
signal input_trailer            : std_logic_vector(63 downto 0);
signal header_crc9_error         :  std_logic;
signal payload_crc20_error       :  std_logic;
signal length_error              :  std_logic;
 
signal spy_we                    :  std_logic;
signal spy_addr                  :  std_logic_vector(addr_width_64 - 1 downto 0); --addr width when 2x 32-bit memories are accessed
signal spy_reset                 :  std_logic;
 
 
signal      ipb_mux_data:  std_logic_vector(31 downto 0);
signal      capture_data_lsw :  std_logic_vector(31 downto 0);
signal      capture_data_msw :  std_logic_vector(31 downto 0);
signal      ipb_strobe_lsw : std_logic; 
signal      ipb_strobe_msw : std_logic;
signal      ipb_rdata_lsw    :  std_logic_vector(31 downto 0);
signal      ipb_rdata_msw    :  std_logic_vector(31 downto 0);
 
signal      ipb_in_lsw:  ipb_wbus;
signal      ipb_out_lsw: ipb_rbus;
signal      ipb_in_msw:  ipb_wbus;
signal      ipb_out_msw: ipb_rbus;
 
begin   
 
fabric: entity work.ipbus_fabric_sel
  generic map(
    NSLV => N_SLAVES,
    SEL_WIDTH => IPBUS_SEL_WIDTH)
  port map(
   ipb_in => ipb_in,
   ipb_out => ipb_out,
 
    sel => ipbus_sel_L1CaloHubRodInputCaptureRegisters(ipb_in.ipb_addr),
    ipb_to_slaves => ipbw,
    ipb_from_slaves => ipbr
  );
 
 
Input_channel_select_reg: entity work.ipbus_reg_v
    port map( 
          clk => ipb_clk,
          reset => ipb_rst,
          ipbus_in => ipbw(N_SLV_input_channel_select),
          ipbus_out => ipbr(N_SLV_input_channel_select),
          q(0) => selected_chan
        );
 
 
 
--pulse reg for arming the capture mech -----
Capture_Control_reg: entity work.ipbus_reg_v
   port map( 
          clk => ipb_clk,
          reset => capture_control_reg_rst,
          ipbus_in => ipbw(N_SLV_INPUT_CAPTURE_CONTROL),
          ipbus_out => ipbr(N_SLV_INPUT_CAPTURE_CONTROL),
          stb(0) => capture_control_reg_stb,
          q(0) => input_capture_control
        );
capture_control_reg_rst <=  capture_control_reg_stb or ipb_rst;  
 
Capture_status_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_INPUT_CAPTURE_STATUS),
          ipb_out => ipbr(N_SLV_INPUT_CAPTURE_STATUS),
          slv_clk => pp_clock,
          d(0) => capture_status,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
 
Header_0_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_HEADER_0),
          ipb_out => ipbr(N_SLV_HEADER_0),
          slv_clk => pp_clock,
          d(0) => input_header(31 downto 0),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
--header_0_i <= "000" & header_0(28 downto 0);  --blank out "version" field
 
Header_1_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_HEADER_1),
          ipb_out => ipbr(N_SLV_HEADER_1),
          slv_clk => pp_clock,
          d(0) => input_header(63 downto 32),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
 
 
trailer_0_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TRAILER_0),
          ipb_out => ipbr(N_SLV_TRAILER_0),
          slv_clk => pp_clock,
          d(0) => input_trailer(31 downto 0),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
trailer_1_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TRAILER_1),
          ipb_out => ipbr(N_SLV_TRAILER_1),
          slv_clk => pp_clock,
          d(0) => input_trailer(63 downto 32),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
pkt_count_reg: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_PKT_COUNT),
          ipb_out => ipbr(N_SLV_PKT_COUNT),
          slv_clk => pp_clock,
          d(0) => pkt_count,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
capture_lsw : ipbus_dpram
   generic map (
        ADDR_WIDTH =>  addr_width_64,
        DATA_WIDTH =>  32
    )
  PORT MAP (
    clk             => ipb_clk,
    rst             => spy_reset,
    ipb_in          => ipb_in_lsw,
    ipb_out         => ipb_out_lsw,
    rclk            => pp_clock,
    we              => spy_we,
    d               => s_tdata(31 downto 0),
    q               => capture_data_lsw,
    addr            => spy_addr
      
  );
 
capture_msw : ipbus_dpram
   generic map (
        ADDR_WIDTH =>  addr_width_64,
        DATA_WIDTH =>  32
    )
  PORT MAP (
    clk             => ipb_clk,
    rst             => spy_reset,
    ipb_in          => ipb_in_msw,
    ipb_out         => ipb_out_msw,
    rclk            => pp_clock,
    we              => spy_we,
    d               => s_tdata(63 downto 32),
    q               => capture_data_msw,
    addr            => spy_addr
      
  );
 
---create ipb_in for the two RAMs ---
ipb_in_lsw.ipb_strobe <= ipbw(N_SLV_TRACE_Memory).ipb_strobe and not ipbw(N_SLV_TRACE_MEMORY).ipb_addr(0);
ipb_in_msw.ipb_strobe <= ipbw(N_SLV_TRACE_Memory).ipb_strobe and     ipbw(N_SLV_TRACE_MEMORY).ipb_addr(0);
 
ipb_in_lsw.ipb_addr(addr_width_64 -1 downto 0)  <=  ipbw(N_SLV_TRACE_MEMORY).ipb_addr((addr_width_64) downto 1);
ipb_in_msw.ipb_addr(addr_width_64 -1 downto 0)  <=  ipbw(N_SLV_TRACE_MEMORY).ipb_addr((addr_width_64) downto 1);
 
ipb_in_lsw.ipb_wdata <=  ipbw(N_SLV_TRACE_MEMORY).ipb_wdata;
ipb_in_msw.ipb_wdata <=  ipbw(N_SLV_TRACE_MEMORY).ipb_wdata;
 
ipb_in_lsw.ipb_write <= ipbw(N_SLV_TRACE_MEMORY).ipb_write and not ipbw(N_SLV_TRACE_MEMORY).ipb_addr(0);
ipb_in_msw.ipb_write <= ipbw(N_SLV_TRACE_MEMORY).ipb_write and     ipbw(N_SLV_TRACE_MEMORY).ipb_addr(0);
 
---create ipb_out for the two RAMs ---
 
with ipbw(N_SLV_TRACE_MEMORY).ipb_addr(0) select 
    ipbr(N_SLV_TRACE_MEMORY).ipb_rdata      <= ipb_out_lsw.ipb_rdata when '0', 
                                               ipb_out_msw.ipb_rdata  when others;
 
 
with ipbw(N_SLV_TRACE_MEMORY).ipb_addr(0) select 
   ipbr(N_SLV_TRACE_MEMORY).ipb_ack          <= ipb_out_lsw.ipb_ack when '0',  
                                                ipb_out_msw.ipb_ack when others;
 
 
with ipbw(N_SLV_TRACE_MEMORY).ipb_addr(0) select  
   ipbr(N_SLV_TRACE_MEMORY).ipb_err           <= ipb_out_lsw.ipb_err when '0',  
                                                ipb_out_msw.ipb_err when others;       
 
 
 
 
spy_reset <= ipb_rst or input_capture_control(1); -- or clear or reset;
 
 
-----capture mech -------------------
 
-------sample the pulse reg in the pp_clock domain ------
--armed_s samples the pulse bit running on ipb_clk
--armed_s_del sample armed_s synchronously on pp_clock
--armed_stat is the user's status flag indicating the mech is armed, but not triggered
 
--clear <= pkt_capture_control(1);
 
input_capture_mech: input_capture
   generic map (
        packet_version   => "001",
        addr_width       => addr_width_64
 
        ) 
  Port map( 
          pp_clock                  => pp_clock,
          ipb_rst                   => ipb_rst,
          input_capture_control     => input_capture_control,
          s_tvalid                  => s_tvalid,
          s_tlast                   => s_tlast,
          s_tdata                   => s_tdata,
          poll_chan                 => poll_chan,
          
          current_chan              => current_chan,
          selected_chan             => selected_chan(4 downto 0),
          timeout_err               => timeout_err,
          pkt_count                 => pkt_count,
      
          input_header              => input_header,
          input_trailer             => input_trailer,
          capture_status            => capture_status,
          header_crc9_error         => open,
          payload_crc20_error       => open,
          length_error              => open,
          spy_we                    => spy_we,
          spy_addr                  => spy_addr 
          
        );
 
 
 
end RTL;