top_rod_jfex Entity Reference

Inheritance diagram for top_rod_jfex:

Entities
rtl	architecture

Libraries
IEEE
unisim

Use Clauses
STD_LOGIC_1164
vcomponents
ipbus

Generics
Module_ID	std_logic_vector ( 31 downto 0 ) := x " 200000ED "
GLOBAL_DATE	std_logic_vector ( 31 downto 0 ) := x " 20230001 "
	Date format DDMMYYYY in decimal.
GLOBAL_TIME	std_logic_vector ( 31 downto 0 ) := x " 00000001 "
	Time format 00HHMMSS in decimal.
GLOBAL_VER	std_logic_vector ( 31 downto 0 ) := x " 00000002 "
	Version of the repository (format: MMmmcccc in hex)
GLOBAL_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000003 "
	Short 7-digit git SHA of the repository.
TOP_VER	std_logic_vector ( 31 downto 0 ) := x " 00000004 "
	Version of the top folder, see TOP_SHA.
TOP_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000005 "
	Short 7-digit git SHA of the top folder: list file, xdcs, XMLs, tcl file and this file.
CON_VER	std_logic_vector ( 31 downto 0 ) := x " 00000006 "
CON_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000007 "
	Short 7-digit git SHA of the Hog submodule.
HOG_VER	std_logic_vector ( 31 downto 0 ) := x " 00000008 "
HOG_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000009 "
	Short 7-digit git SHA of the Hog submodule.
XML_SHA	std_logic_vector ( 31 downto 0 ) := x " 0000000a "
	Short 7-digit git SHA of the XMLs.
XML_VER	std_logic_vector ( 31 downto 0 ) := x " 0000000b "
	Version of the XMLs.
ROD_EEX_SHA	std_logic_vector ( 31 downto 0 ) := x " 0000000c "
ROD_EFEX_VER	std_logic_vector ( 31 downto 0 ) := x " 0000000d "
ROD_JFEX_SHA	std_logic_vector ( 31 downto 0 ) := x " 0000000c "
ROD_JFEX_VER	std_logic_vector ( 31 downto 0 ) := x " 0000000d "
CRC20_G_Poly	std_logic_vector ( 19 downto 0 ) := x " 8359f "
jfex_rod	integer := 1
efex_rod	integer := 0
golden_rod	integer := 0
tob_0_flx_bp_link	integer := 0
bulk_0_flx_bp_link	integer := 1
bulk_1_flx_bp_link	integer := 2
bulk_2_flx_bp_link	integer := 3
debug	integer := 0
alt_cttc	integer := 1
C_S_AXI_DATA_WIDTH	integer := 32
C_S_AXI_ADDR_WIDTH	integer := 9

Ports
CLK_125_pin	in	std_logic
CLK_40_pin_P	in	std_logic
CLK_40_pin_N	in	std_logic
gtx_clk_bufg_out	out	std_logic
phy_resetn	out	std_logic
rgmii_txd	out	std_logic_vector ( 3 downto 0 )
rgmii_tx_ctl	out	std_logic
rgmii_txc	out	std_logic
rgmii_rxd	in	std_logic_vector ( 3 downto 0 )
rgmii_rx_ctl	in	std_logic
rgmii_rxc	in	std_logic
mdio	inout	std_logic
mdc	out	std_logic
reset_error	in	std_logic
leds	out	std_logic_vector ( 1 downto 0 )
userled	out	std_logic
rotary_switch	in	std_logic_vector ( 3 downto 0 )
gp_button	in	std_logic
t_wrn_b	in	std_logic
smbalert_b	in	std_logic
ck_pll_lock	in	std_logic
ck_int	in	std_logic
phy_int	in	std_logic
t_pod0_int	in	std_logic
t_pod1_int	in	std_logic
t_pod2_int	in	std_logic
r_pod_int	in	std_logic
loc_addr1	in	std_logic
loc_addr2	in	std_logic
loc_addr3	in	std_logic
loc_addr4	in	std_logic
loc_addr5	in	std_logic
loc_addr6	in	std_logic
loc_addr7	in	std_logic
loc_addr8	in	std_logic
lemo	out	std_logic
t_pod0_rst_b	out	std_logic
t_pod1_rst_b	out	std_logic
t_pod2_rst_b	out	std_logic
r_pod_rst_b	out	std_logic
EMC_INTF_addr	out	STD_LOGIC_VECTOR ( 28 downto 0 )
EMC_INTF_ce_n	out	STD_LOGIC_VECTOR ( 0 to 0 )
EMC_INTF_oen	out	STD_LOGIC_VECTOR ( 0 to 0 )
EMC_INTF_wen	out	STD_LOGIC
emc_intf_dq_io	inout	STD_LOGIC_VECTOR ( 15 downto 0 )
iic_1_scl_io	inout	STD_LOGIC
iic_1_sda_io	inout	STD_LOGIC
iic_scl_io	inout	STD_LOGIC
iic_sda_io	inout	STD_LOGIC
CK_SPI_MOSI	inout	STD_LOGIC
CK_SPI_MISO	inout	STD_LOGIC
CK_SPI_CK	inout	STD_LOGIC
CK_SPI_LE	out	STD_LOGIC
Vp_Vn_v_n	in	STD_LOGIC
Vp_Vn_v_p	in	STD_LOGIC
GTCLK_q112_c0p	in	STD_LOGIC
GTCLK_q112_c0n	in	STD_LOGIC
GTCLK_q115_c0p	in	STD_LOGIC
GTCLK_q115_c0n	in	STD_LOGIC
GTCLK_q118_c0p	in	STD_LOGIC
GTCLK_q118_c0n	in	STD_LOGIC
GTCLK_q211_c0p	in	STD_LOGIC
GTCLK_q211_c0n	in	STD_LOGIC
GTCLK_q214_c0p	in	STD_LOGIC
GTCLK_q214_c0n	in	STD_LOGIC
GTCLK_q217_c0p	in	STD_LOGIC
GTCLK_q217_c0n	in	STD_LOGIC
GTCLK_q219_c0p	in	STD_LOGIC
GTCLK_q219_c0n	in	STD_LOGIC
GTCLK_q218_c1p	in	STD_LOGIC
GTCLK_q218_c1n	in	STD_LOGIC
RXP_0	in	STD_LOGIC
RXN_0	in	STD_LOGIC
RXP_1	in	STD_LOGIC
RXN_1	in	STD_LOGIC
RXP_2	in	STD_LOGIC
RXN_2	in	STD_LOGIC
RXP_3	in	STD_LOGIC
RXN_3	in	STD_LOGIC
RXP_4	in	STD_LOGIC
RXN_4	in	STD_LOGIC
RXP_5	in	STD_LOGIC
RXN_5	in	STD_LOGIC
RXP_6	in	STD_LOGIC
RXN_6	in	STD_LOGIC
RXP_7	in	STD_LOGIC
RXN_7	in	STD_LOGIC
RXP_8	in	STD_LOGIC
RXN_8	in	STD_LOGIC
RXP_9	in	STD_LOGIC
RXN_9	in	STD_LOGIC
RXP_10	in	STD_LOGIC
RXN_10	in	STD_LOGIC
RXP_11	in	STD_LOGIC
RXN_11	in	STD_LOGIC
RXP_12	in	STD_LOGIC
RXN_12	in	STD_LOGIC
RXP_13	in	STD_LOGIC
RXN_13	in	STD_LOGIC
RXP_14	in	STD_LOGIC
RXN_14	in	STD_LOGIC
RXP_15	in	STD_LOGIC
RXN_15	in	STD_LOGIC
RXP_16	in	STD_LOGIC
RXN_16	in	STD_LOGIC
RXP_17	in	STD_LOGIC
RXN_17	in	STD_LOGIC
RXP_18	in	STD_LOGIC
RXN_18	in	STD_LOGIC
RXP_19	in	STD_LOGIC
RXN_19	in	STD_LOGIC
RXP_20	in	STD_LOGIC
RXN_20	in	STD_LOGIC
RXP_21	in	STD_LOGIC
RXN_21	in	STD_LOGIC
RXP_22	in	STD_LOGIC
RXN_22	in	STD_LOGIC
RXP_23	in	STD_LOGIC
RXN_23	in	STD_LOGIC
RO_CTRL_TXN	out	std_logic
RO_CTRL_TXP	out	std_logic
RXP_ttc	in	std_logic
RXN_ttc	in	std_logic
CTTC_rxp_alt	in	std_logic
CTTC_rxn_alt	in	std_logic
fm1_gttxn_out	out	std_logic_vector ( 1 downto 0 )
fm1_gttxp_out	out	std_logic_vector ( 1 downto 0 )
fm2_gttxn_out	out	std_logic_vector ( 1 downto 0 )
fm2_gttxp_out	out	std_logic_vector ( 1 downto 0 )
CK_PWR_DNB	out	std_logic
REF_CLK_SEL	out	std_logic
CK_SYNCB	out	std_logic
PWR_CON3	out	std_logic
PWR_CON4	out	std_logic

Detailed Description

Definition at line 46 of file top_rod_jfex.vhd.

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The documentation for this class was generated from the following file:

• ROD/rod_jfex/hdl/top_rod_jfex.vhd