rtl Architecture Reference

Components
backplane_control_ila
packet_processor_clock
ROD_system
jfex_backplane
axi_ch0
fex_rx_checker	<Entity fex_rx_checker>
packet_processor	<Entity packet_processor>
system_top_reset	<Entity system_top_reset>
reset_count	<Entity reset_count>
IBUF
pp_ctrl_vio
FM_ROD
Full_Mode_Tx
Full_Mode_CTTC
packet_fifo	<Entity packet_fifo>
vio_top
ila_hub_rst
vio_ttc

Signals
ipbr_backplane	ipb_rbus
ipbw_backplane	ipb_wbus
ipbr_Processor	ipb_rbus
ipbw_Processor	ipb_wbus
ipb_clk	std_logic
ipb_rst	std_logic
geo_location	STD_LOGIC_VECTOR ( 7 downto 0 )
flx_bp_bus	STD_LOGIC_VECTOR ( 11 downto 0 )
pp_clock	std_logic
rt_clk	std_logic
backplane_control	std_logic_vector ( 31 downto 0 )
cttc_cpllreset_in	std_logic
cttc_cpllpd_in	STD_LOGIC
cttc_rxbufreset_in	STD_LOGIC
cttc_rxpcsreset_in	STD_LOGIC
cttc_rxpmareset_in	STD_LOGIC
cttc_rxcdrhold_in	STD_LOGIC
cttc_rxpd_in	STD_LOGIC
PKT_CLK	STD_LOGIC
CLK_40	STD_LOGIC
clk_160	std_logic
CLK_40_pin	STD_LOGIC
CLK_125	STD_LOGIC
gp_button_i	STD_LOGIC
GTCLK_q218	STD_LOGIC
bulk_m_tvalid_0	STD_LOGIC
bulk_m_tlast_0	STD_LOGIC
bulk_m_tdata_0	STD_LOGIC_VECTOR ( 63 downto 0 )
bulk_m_header_marker_0	STD_LOGIC
bulk_m_tail_marker_0	STD_LOGIC
bulk_m_tready_0	STD_LOGIC
bulk_fm_tvalid_0	STD_LOGIC
bulk_fm_tlast_0	STD_LOGIC
bulk_fm_tdata_0	STD_LOGIC_VECTOR ( 31 downto 0 )
bulk_fm_tready_0	STD_LOGIC
flx_bp_240_bulk_0	STD_LOGIC
bulk_m_tvalid_1	STD_LOGIC
bulk_m_tlast_1	STD_LOGIC
bulk_m_tdata_1	STD_LOGIC_VECTOR ( 63 downto 0 )
bulk_m_header_marker_1	STD_LOGIC
bulk_m_tail_marker_1	STD_LOGIC
bulk_m_tready_1	STD_LOGIC
bulk_fm_tvalid_1	STD_LOGIC
bulk_fm_tlast_1	STD_LOGIC
bulk_fm_tdata_1	STD_LOGIC_VECTOR ( 31 downto 0 )
bulk_fm_tready_1	STD_LOGIC
flx_bp_240_bulk_1	STD_LOGIC
bulk_m_tvalid_2	STD_LOGIC
bulk_m_tlast_2	STD_LOGIC
bulk_m_tdata_2	STD_LOGIC_VECTOR ( 63 downto 0 )
bulk_m_header_marker_2	STD_LOGIC
bulk_m_tail_marker_2	STD_LOGIC
bulk_m_tready_2	STD_LOGIC
bulk_fm_tvalid_2	STD_LOGIC
bulk_fm_tlast_2	STD_LOGIC
bulk_fm_tdata_2	STD_LOGIC_VECTOR ( 31 downto 0 )
bulk_fm_tready_2	STD_LOGIC
flx_bp_240_bulk_2	STD_LOGIC
FM1_reset_0	STD_LOGIC
FM1_reset_1	STD_LOGIC
FM2_reset_0	STD_LOGIC
FM2_reset_1	STD_LOGIC
fm_soft_reset	STD_LOGIC
stage_fifo_level_tob_0	STD_LOGIC_VECTOR ( 31 downto 0 )
stage_fifo_level_bulk_0	STD_LOGIC_VECTOR ( 31 downto 0 )
stage_fifo_level_bulk_1	STD_LOGIC_VECTOR ( 31 downto 0 )
stage_fifo_level_bulk_2	STD_LOGIC_VECTOR ( 31 downto 0 )
stage_fifo_full_tob_0	std_logic
stage_fifo_full_bulk_0	std_logic
stage_fifo_full_bulk_1	std_logic
stage_fifo_full_bulk_2	std_logic
stage_fifo_busy_tob_0	std_logic
stage_fifo_busy_bulk_0	std_logic
stage_fifo_busy_bulk_1	std_logic
stage_fifo_busy_bulk_2	std_logic
stage_fifo_xoff_tob_0	std_logic
stage_fifo_xoff_bulk_0	std_logic
stage_fifo_xoff_bulk_1	std_logic
stage_fifo_xoff_bulk_2	std_logic
flx_backpressure_tob_0	STD_LOGIC
flx_backpressure_bulk_0	STD_LOGIC
flx_backpressure_bulk_1	STD_LOGIC
flx_backpressure_bulk_2	STD_LOGIC
CHANNEL_CTRL_0	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_0	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_0	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_0	STD_LOGIC
m_axi_rx_tlast_0	STD_LOGIC
m_axi_rx_tkeep_0	std_logic_vector ( 7 downto 0 )
m_axi_ufc_rx_tdata_0	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_0	STD_LOGIC
m_axi_ufc_rx_tlast_0	STD_LOGIC
user_clk_out_0	STD_LOGIC
CHANNEL_CTRL_1	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_1	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_1	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_1	STD_LOGIC
m_axi_rx_tlast_1	STD_LOGIC
m_axi_rx_tkeep_1	std_logic_vector ( 7 downto 0 )
m_axi_ufc_rx_tdata_1	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_1	STD_LOGIC
m_axi_ufc_rx_tlast_1	STD_LOGIC
user_clk_out_1	STD_LOGIC
CHANNEL_CTRL_2	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_2	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_2	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_2	STD_LOGIC
m_axi_rx_tlast_2	STD_LOGIC
m_axi_rx_tkeep_2	std_logic_vector ( 7 downto 0 )
m_axi_ufc_rx_tdata_2	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_2	STD_LOGIC
m_axi_ufc_rx_tlast_2	STD_LOGIC
user_clk_out_2	STD_LOGIC
CHANNEL_CTRL_3	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_3	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_3	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_3	STD_LOGIC
m_axi_rx_tlast_3	STD_LOGIC
m_axi_ufc_rx_tdata_3	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_3	STD_LOGIC
m_axi_ufc_rx_tlast_3	STD_LOGIC
user_clk_out_3	STD_LOGIC
CHANNEL_CTRL_4	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_4	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_4	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_4	STD_LOGIC
m_axi_rx_tlast_4	STD_LOGIC
m_axi_ufc_rx_tdata_4	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_4	STD_LOGIC
m_axi_ufc_rx_tlast_4	STD_LOGIC
user_clk_out_4	STD_LOGIC
CHANNEL_CTRL_5	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_5	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_5	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_5	STD_LOGIC
m_axi_rx_tlast_5	STD_LOGIC
m_axi_ufc_rx_tdata_5	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_5	STD_LOGIC
m_axi_ufc_rx_tlast_5	STD_LOGIC
user_clk_out_5	STD_LOGIC
CHANNEL_CTRL_6	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_6	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_6	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_6	STD_LOGIC
m_axi_rx_tlast_6	STD_LOGIC
m_axi_ufc_rx_tdata_6	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_6	STD_LOGIC
m_axi_ufc_rx_tlast_6	STD_LOGIC
user_clk_out_6	STD_LOGIC
CHANNEL_CTRL_7	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_7	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_7	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_7	STD_LOGIC
m_axi_rx_tlast_7	STD_LOGIC
m_axi_ufc_rx_tdata_7	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_7	STD_LOGIC
m_axi_ufc_rx_tlast_7	STD_LOGIC
user_clk_out_7	STD_LOGIC
CHANNEL_CTRL_8	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_8	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_8	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_8	STD_LOGIC
m_axi_rx_tlast_8	STD_LOGIC
m_axi_ufc_rx_tdata_8	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_8	STD_LOGIC
m_axi_ufc_rx_tlast_8	STD_LOGIC
user_clk_out_8	STD_LOGIC
CHANNEL_CTRL_9	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_9	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_9	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_9	STD_LOGIC
m_axi_rx_tlast_9	STD_LOGIC
m_axi_ufc_rx_tdata_9	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_9	STD_LOGIC
m_axi_ufc_rx_tlast_9	STD_LOGIC
user_clk_out_9	STD_LOGIC
CHANNEL_CTRL_10	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_10	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_10	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_10	STD_LOGIC
m_axi_rx_tlast_10	STD_LOGIC
m_axi_ufc_rx_tdata_10	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_10	STD_LOGIC
m_axi_ufc_rx_tlast_10	STD_LOGIC
user_clk_out_10	STD_LOGIC
CHANNEL_CTRL_11	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_11	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_11	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_11	STD_LOGIC
m_axi_rx_tlast_11	STD_LOGIC
m_axi_ufc_rx_tdata_11	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_11	STD_LOGIC
m_axi_ufc_rx_tlast_11	STD_LOGIC
user_clk_out_11	STD_LOGIC
CHANNEL_CTRL_12	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_12	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_12	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_12	STD_LOGIC
m_axi_rx_tlast_12	STD_LOGIC
m_axi_ufc_rx_tdata_12	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_12	STD_LOGIC
m_axi_ufc_rx_tlast_12	STD_LOGIC
user_clk_out_12	STD_LOGIC
free_clk_out_12	STD_LOGIC
CHANNEL_CTRL_13	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_13	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_13	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_13	STD_LOGIC
m_axi_rx_tlast_13	STD_LOGIC
m_axi_ufc_rx_tdata_13	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_13	STD_LOGIC
m_axi_ufc_rx_tlast_13	STD_LOGIC
user_clk_out_13	STD_LOGIC
free_clk_out_13	STD_LOGIC
CHANNEL_CTRL_14	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_14	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_14	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_14	STD_LOGIC
m_axi_rx_tlast_14	STD_LOGIC
m_axi_ufc_rx_tdata_14	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_14	STD_LOGIC
m_axi_ufc_rx_tlast_14	STD_LOGIC
user_clk_out_14	STD_LOGIC
free_clk_out_14	STD_LOGIC
CHANNEL_CTRL_15	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_15	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_15	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_15	STD_LOGIC
m_axi_rx_tlast_15	STD_LOGIC
m_axi_ufc_rx_tdata_15	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_15	STD_LOGIC
m_axi_ufc_rx_tlast_15	STD_LOGIC
user_clk_out_15	STD_LOGIC
free_clk_out_15	STD_LOGIC
CHANNEL_CTRL_16	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_16	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_16	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_16	STD_LOGIC
m_axi_rx_tlast_16	STD_LOGIC
m_axi_ufc_rx_tdata_16	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_16	STD_LOGIC
m_axi_ufc_rx_tlast_16	STD_LOGIC
user_clk_out_16	STD_LOGIC
CHANNEL_CTRL_17	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_17	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_17	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_17	STD_LOGIC
m_axi_rx_tlast_17	STD_LOGIC
m_axi_ufc_rx_tdata_17	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_17	STD_LOGIC
m_axi_ufc_rx_tlast_17	STD_LOGIC
user_clk_out_17	STD_LOGIC
CHANNEL_CTRL_18	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_18	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_18	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_18	STD_LOGIC
m_axi_rx_tlast_18	STD_LOGIC
m_axi_ufc_rx_tdata_18	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_18	STD_LOGIC
m_axi_ufc_rx_tlast_18	STD_LOGIC
user_clk_out_18	STD_LOGIC
CHANNEL_CTRL_19	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_19	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_19	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_19	STD_LOGIC
m_axi_rx_tlast_19	STD_LOGIC
m_axi_ufc_rx_tdata_19	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_19	STD_LOGIC
m_axi_ufc_rx_tlast_19	STD_LOGIC
user_clk_out_19	STD_LOGIC
CHANNEL_CTRL_20	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_20	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_20	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_20	STD_LOGIC
m_axi_rx_tlast_20	STD_LOGIC
m_axi_ufc_rx_tdata_20	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_20	STD_LOGIC
m_axi_ufc_rx_tlast_20	STD_LOGIC
user_clk_out_20	STD_LOGIC
CHANNEL_CTRL_21	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_21	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_21	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_21	STD_LOGIC
m_axi_rx_tlast_21	STD_LOGIC
m_axi_ufc_rx_tdata_21	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_21	STD_LOGIC
m_axi_ufc_rx_tlast_21	STD_LOGIC
user_clk_out_21	STD_LOGIC
CHANNEL_CTRL_22	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_22	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_22	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_22	STD_LOGIC
m_axi_rx_tlast_22	STD_LOGIC
m_axi_ufc_rx_tdata_22	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_22	STD_LOGIC
m_axi_ufc_rx_tlast_22	STD_LOGIC
user_clk_out_22	STD_LOGIC
CHANNEL_CTRL_23	STD_LOGIC_VECTOR ( 31 downto 0 )
CHANNEL_STAT_23	STD_LOGIC_VECTOR ( 31 downto 0 )
m_axi_rx_tdata_23	std_logic_vector ( 63 downto 0 )
m_axi_rx_tvalid_23	STD_LOGIC
m_axi_rx_tlast_23	STD_LOGIC
m_axi_ufc_rx_tdata_23	STD_LOGIC_vector ( 63 downto 0 )
m_axi_ufc_rx_tvalid_23	STD_LOGIC
m_axi_ufc_rx_tlast_23	STD_LOGIC
user_clk_out_23	STD_LOGIC
channel_enable_vio	std_logic_vector ( 23 downto 0 )
first_chan_vio	std_logic_vector ( 4 downto 0 )
last_chan_vio	std_logic_vector ( 4 downto 0 )
TTC_ignore_vio	std_logic
debug_ctrl_vio	std_logic
pp0_m_axi_tdata	std_logic_vector ( 63 downto 0 )
pp0_m_axi_tvalid	STD_LOGIC
pp0_m_axi_tlast	STD_LOGIC
pp0_m_axi_tready	STD_LOGIC
pp_soft_reset_vio	STD_LOGIC
pp_reset	STD_LOGIC
fifo_AXI4_TDATA	std_logic_vector ( 31 downto 0 )
fifo_AXI4_TVALID	STD_LOGIC
felix_AXI4_TREADY	STD_LOGIC
fifo_AXI4_tlast	STD_LOGIC
ppout_fifo_AXI4_TDATA	std_logic_vector ( 31 downto 0 )
ppout_fifo_AXI4_TVALID	STD_LOGIC
felix_ch1_AXI4_TREADY	STD_LOGIC
ppout_fifo_AXI4_tlast	STD_LOGIC
flx_bp_240_tob_0	STD_LOGIC
FM_TXOUTCLK	STD_LOGIC
FM_TXOUTCLK_2	STD_LOGIC
GTREFCLK_Q217_C0	STD_LOGIC
gp_button_ibuf	STD_LOGIC
vio_reset	STD_LOGIC
sys_top_reset	STD_LOGIC
MASTER_RESET	STD_LOGIC
rx_GTReset	STD_LOGIC
rx_reset	STD_LOGIC
ttc_word_0	std_logic_vector ( 31 downto 0 )
ttc_word_1	std_logic_vector ( 31 downto 0 )
ttc_word_2	std_logic_vector ( 31 downto 0 )
ttc_word_3	std_logic_vector ( 31 downto 0 )
ttc_seq	std_logic_vector ( 1 downto 0 )
cttc_usrclk	std_logic
L1A	std_logic
l1id_mis_stretch	std_logic
vio_chan_reset	std_logic
sys_top_reset_b	std_logic
spi_pwr2	std_logic
spi_pwr1	std_logic := ' 0 '
ro_user_clock	STD_LOGIC
ro_controller_reset	STD_LOGIC
ro_txcharisk	std_logic_vector ( 3 downto 0 )
ro_txdata	std_logic_vector ( 31 downto 0 )
ro_status	std_logic_vector ( 7 downto 0 )
ttc_status	std_logic_vector ( 31 downto 0 )
ttc_reset	std_logic
hub_link_reset	std_logic
multichannel_busy	std_logic
combined_busy	std_logic
lemo_i	std_logic
full_mode_stat_tob_0	std_logic_vector ( 31 downto 0 )
full_mode_stat_bulk_0	std_logic_vector ( 31 downto 0 )
full_mode_stat_bulk_1	std_logic_vector ( 31 downto 0 )
full_mode_stat_bulk_2	std_logic_vector ( 31 downto 0 )
FM_L1id_stat_tob_0	std_logic_vector ( 31 downto 0 )
FM_L1id_stat_bulk_0	std_logic_vector ( 31 downto 0 )
FM_L1id_stat_bulk_1	std_logic_vector ( 31 downto 0 )
FM_L1id_stat_bulk_2	std_logic_vector ( 31 downto 0 )
full_mode_ctrl_tob_0	std_logic_vector ( 31 downto 0 )
full_mode_ctrl_bulk_0	std_logic_vector ( 31 downto 0 )
full_mode_ctrl_bulk_1	std_logic_vector ( 31 downto 0 )
full_mode_ctrl_bulk_2	std_logic_vector ( 31 downto 0 )
hub_link_reset_b	std_logic
hub_reset	std_logic
hub_rst_tmr	std_logic
gt_refclk_q219_c0	std_logic
FM_CTTC_rxdata	std_logic_vector ( 31 downto 0 )
FM_CTTC_rxcharisk	std_logic_vector ( 3 downto 0 )
FM_CTTC_MGT_bus	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
FM_CTTC_rxoutclk	std_logic
BP_CTTC_rxdata	std_logic_vector ( 31 downto 0 )
BP_CTTC_rxcharisk	std_logic_vector ( 3 downto 0 )
BP_CTTC_MGT_bus	STD_LOGIC_VECTOR ( 31 DOWNTO 0 )
BP_CTTC_rxoutclk	std_logic
ttc_mux_ctrl	std_logic

Instantiations
reset_top	system_top_reset <Entity system_top_reset>
phy_reset	system_top_reset <Entity system_top_reset>
proc_clock_gen	packet_processor_clock
top_vio	vio_top
ipbus_blk	rod_system
backplane	jfex_backplane
ila_axi_chan_0	fex_rx_checker <Entity fex_rx_checker>
ila_axi_chan_12	fex_rx_checker <Entity fex_rx_checker>
ila_axi_chan_13	fex_rx_checker <Entity fex_rx_checker>
ila_axi_chan_14	fex_rx_checker <Entity fex_rx_checker>
ila_axi_chan_15	fex_rx_checker <Entity fex_rx_checker>
ila_axi_chan_4	axi_ch0
ila_axi_chan_5	axi_ch0
ila_axi_chan_6	axi_ch0
ila_axi_chan_7	axi_ch0
vio_pp_ctrl	pp_ctrl_vio
event_builder	packet_processor <Entity packet_processor>
ttc_source_sel	vio_ttc
fm_interface_1	full_mode_tx
fm_interface_2	full_mode_tx
fm_interface_3	full_mode_cttc
bulk_0_64_32	packet_fifo <Entity packet_fifo>
bulk_1_64_32	packet_fifo <Entity packet_fifo>
bulk_2_64_32	packet_fifo <Entity packet_fifo>
pp_out_fifo_6432	packet_fifo <Entity packet_fifo>
clk125_buf	ibuf
clk_40_ibuf	ibufds
spi_pwr	reset_count <Entity reset_count>
ck_pwr_dnb_buf	obuf
ck_spi_le_buf	obuf
ref_ck_sel_buf	obuf
ck_syncb_buf	obuf
pwr_con3_buf	obuf
pwr_con4_buf	obuf
ibufds_q218	ibufds_gte2
button_ibuf	ibuf
lemo_obuf	obuf
ibufds_gte2_q219_c0	ibufds_gte2
bkpln_control_ila	backplane_control_ila

Detailed Description

Definition at line 386 of file top_rod_jfex.vhd.

---

The documentation for this class was generated from the following file:

• ROD/rod_jfex/hdl/top_rod_jfex.vhd