ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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top_rod_jfex.vhd
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1 
37 
38 library IEEE;
39 use IEEE.STD_LOGIC_1164.ALL;
40 
41 library unisim;
42 use unisim.vcomponents.all;
43 use work.ipbus.ALL;
44 
45 
46 entity top_rod_jfex is
47  generic (
48  Module_ID : std_logic_vector (31 downto 0) := x"200000ED";
49  --bit31: reserved
50  --bit30: rod_efex
51  --bit29: rod_jfex
52  --bit28: golden image
53 
54  -- pcbUpdate = x"4" --this is stored in NOVO memory, but any board in circulation will be rev 4
55  -- issue = x"0" -- not defined today
56  -- serial = x"00" --this is stored in the novo ram so perhaps this should be read from there via software
57  -- L1CaloNumber = x"0ed0" --this is a made up number
58  -- module id = x"400000ed"
59  -- Global Generic Variables
61  GLOBAL_DATE : std_logic_vector(31 downto 0) := x"20230001";
63  GLOBAL_TIME : std_logic_vector(31 downto 0) := x"00000001";
65  GLOBAL_VER : std_logic_vector(31 downto 0) := x"00000002";
67  GLOBAL_SHA : std_logic_vector(31 downto 0) := x"00000003";
69  TOP_VER : std_logic_vector(31 downto 0) := x"00000004";
71  TOP_SHA : std_logic_vector(31 downto 0) := x"00000005";
72  CON_VER : std_logic_vector(31 downto 0) := x"00000006";
74  CON_SHA : std_logic_vector(31 downto 0) := x"00000007";
75  HOG_VER : std_logic_vector(31 downto 0) := x"00000008";
77  HOG_SHA : std_logic_vector(31 downto 0) := x"00000009";
78 
79  --IPBus XML
81  XML_SHA : std_logic_vector(31 downto 0) := x"0000000a";
83  XML_VER : std_logic_vector(31 downto 0) := x"0000000b";
84 
85  ROD_EEX_SHA : std_logic_vector(31 downto 0) := x"0000000c";
86  ROD_EFEX_VER : std_logic_vector(31 downto 0) := x"0000000d";
87 
88  ROD_JFEX_SHA : std_logic_vector(31 downto 0) := x"0000000c";
89  ROD_JFEX_VER : std_logic_vector(31 downto 0) := x"0000000d";
90 
91  -- CRC20_G_Poly : std_logic_vector(19 downto 0) := x"8349f"; --old poly
92  CRC20_G_Poly : std_logic_vector(19 downto 0) := x"8359f"; --correct poly
93  jfex_rod : integer := 1;
94  efex_rod : integer := 0;
95  golden_rod : integer := 0;
96 
97  tob_0_flx_bp_link : integer := 0;
98  bulk_0_flx_bp_link : integer := 1;
99  bulk_1_flx_bp_link : integer := 2;
100  bulk_2_flx_bp_link : integer := 3;
101  debug : integer := 0;
102  alt_cttc : integer := 1;
103 -- XmlVersion : std_logic_vector (31 downto 0) := x"20200309";
104  -- BuildTimeAndDate : std_logic_vector (31 downto 0) := x"20200326";
105  -- FirmwareVersion : std_logic_vector (31 downto 0) := x"20200319";
106  -- User parameters ends
107  -- Do not modify the parameters beyond this line
108  -- Users to add parameters here
109 
110  -- User parameters ends
111  -- Do not modify the parameters beyond this line
112 
113  -- Width of S_AXI data bus
114  C_S_AXI_DATA_WIDTH : integer := 32;
115  -- Width of S_AXI address bus
116  C_S_AXI_ADDR_WIDTH : integer := 9
117  );
118 
119  port (
120 
121 -- ipbus system ports
122 
123  CLK_125_pin : in std_logic;
124  CLK_40_pin_P : in std_logic;
125  CLK_40_pin_N : in std_logic;
126 
127  -- 125 MHZ clock output from MMCM to test pin
128  gtx_clk_bufg_out : out std_logic;
129  phy_resetn : out std_logic;
130 
131  -- RGMII Interface
132  ------------------
133  rgmii_txd : out std_logic_vector(3 downto 0);
134  rgmii_tx_ctl : out std_logic;
135  rgmii_txc : out std_logic;
136  rgmii_rxd : in std_logic_vector(3 downto 0);
137  rgmii_rx_ctl : in std_logic;
138  rgmii_rxc : in std_logic;
139 
140  -- MDIO Interface
141  -----------------
142  mdio : inout std_logic;
143  mdc : out std_logic;
144  reset_error : in std_logic;
145 
146  --LEDs
147  -----------------
148  leds : out std_logic_vector(1 downto 0);
149  userled : out std_logic;
150  rotary_switch : in std_logic_vector(3 downto 0);
151 
152 
153  -- GPIO Interface
154  -------------------
155  gp_button : in std_logic;
156 -- test1_2 : in std_logic;
157 -- test1_3 : in std_logic;
158 -- test1_4 : in std_logic;
159 -- test1_5 : in std_logic;
160  t_wrn_b : in std_logic;
161  smbalert_b : in std_logic;
162  -- gpio2_tri_i(7) => ,
163  -- gpio2_tri_i(8) => ,
164  ck_pll_lock : in std_logic;
165  ck_int : in std_logic;
166  phy_int : in std_logic;
167  t_pod0_int : in std_logic;
168  t_pod1_int : in std_logic;
169  t_pod2_int : in std_logic;
170  r_pod_int : in std_logic;
171  loc_addr1 : in std_logic;
172  loc_addr2 : in std_logic;
173  loc_addr3 : in std_logic;
174  loc_addr4 : in std_logic;
175  loc_addr5 : in std_logic;
176  loc_addr6 : in std_logic;
177  loc_addr7 : in std_logic;
178  loc_addr8 : in std_logic;
179 
180 -- rod_gp_led : out std_logic;
181 -- FP_GP_LED_B : out std_logic;
182 -- FP_RUN_LED_B : out std_logic;
183  lemo : out std_logic;
184  -- gpio_tri_o(4) => ,
185 -- pwr_con3 : out std_logic;
186 
187  -- gpio_tri_o(7) => ,
188 -- ck_pwr_dnb : out std_logic;
189 -- ref_clk_sel : out std_logic;
190 -- ck_syncb : out std_logic;
191 -- phy_rst_n : out std_logic;
192  t_pod0_rst_b : out std_logic;
193  t_pod1_rst_b : out std_logic;
194  t_pod2_rst_b : out std_logic;
195  r_pod_rst_b : out std_logic;
196 
197  --Configuration Flash Interface
198  ---------------------------------
199  EMC_INTF_addr : out STD_LOGIC_VECTOR ( 28 downto 0 );
200  EMC_INTF_ce_n : out STD_LOGIC_VECTOR ( 0 to 0 );
201  EMC_INTF_oen : out STD_LOGIC_VECTOR ( 0 to 0 );
202  EMC_INTF_wen : out STD_LOGIC;
203  emc_intf_dq_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
204 
205  --I2C 1,0 interface
206  ----------------------------------
207  iic_1_scl_io : inout STD_LOGIC;
208  iic_1_sda_io : inout STD_LOGIC;
209  iic_scl_io : inout STD_LOGIC;
210  iic_sda_io : inout STD_LOGIC;
211 
212  --SPI Interface
213  ------------------------------------
214  CK_SPI_MOSI : inout STD_LOGIC; --MOSI
215  CK_SPI_MISO : inout STD_LOGIC; --MISO
216  CK_SPI_CK : inout STD_LOGIC;
217  CK_SPI_LE : out STD_LOGIC;
218 
219  --XADC interface
220  --------------------------------------
221  Vp_Vn_v_n : in STD_LOGIC;
222  Vp_Vn_v_p : in STD_LOGIC;
223 
224 
225 -- -----------------------------------------------------------------
226 -- -- backplane interfce --
227 -- ------------------------------------------------------------------
228 --GT ref clocks
229  GTCLK_q112_c0p : in STD_LOGIC;
230  GTCLK_q112_c0n : in STD_LOGIC;
231 
232  GTCLK_q115_c0p : in STD_LOGIC;
233  GTCLK_q115_c0n : in STD_LOGIC;
234 
235  GTCLK_q118_c0p : in STD_LOGIC;
236  GTCLK_q118_c0n : in STD_LOGIC;
237 
238  GTCLK_q211_c0p : in STD_LOGIC;
239  GTCLK_q211_c0n : in STD_LOGIC;
240 
241  GTCLK_q214_c0p : in STD_LOGIC;
242  GTCLK_q214_c0n : in STD_LOGIC;
243 
244  GTCLK_q217_c0p : in STD_LOGIC;
245  GTCLK_q217_c0n : in STD_LOGIC;
246 
247 -- GTCLK_q218_c0p : in STD_LOGIC;
248 -- GTCLK_q218_c0n : in STD_LOGIC;
249 
250  GTCLK_q219_c0p : in STD_LOGIC;
251  GTCLK_q219_c0n : in STD_LOGIC;
252 
253 
254  GTCLK_q218_c1p : in STD_LOGIC;
255  GTCLK_q218_c1n : in STD_LOGIC;
256 
257 -- GTCLK_q118_c1p : in STD_LOGIC;
258 -- GTCLK_q118_c1n : in STD_LOGIC;
259 
260  -- GTCLK_q111_c1p : in STD_LOGIC;
261  -- GTCLK_q111_c1n : in STD_LOGIC;
262 
263 
264  RXP_0 : in STD_LOGIC;
265  RXN_0 : in STD_LOGIC;
266  RXP_1 : in STD_LOGIC;
267  RXN_1 : in STD_LOGIC;
268  RXP_2 : in STD_LOGIC;
269  RXN_2 : in STD_LOGIC;
270  RXP_3 : in STD_LOGIC;
271  RXN_3 : in STD_LOGIC;
272  RXP_4 : in STD_LOGIC;
273  RXN_4 : in STD_LOGIC;
274  RXP_5 : in STD_LOGIC;
275  RXN_5 : in STD_LOGIC;
276  RXP_6 : in STD_LOGIC;
277  RXN_6 : in STD_LOGIC;
278  RXP_7 : in STD_LOGIC;
279  RXN_7 : in STD_LOGIC;
280  RXP_8 : in STD_LOGIC;
281  RXN_8 : in STD_LOGIC;
282  RXP_9 : in STD_LOGIC;
283  RXN_9 : in STD_LOGIC;
284  RXP_10 : in STD_LOGIC;
285  RXN_10 : in STD_LOGIC;
286  RXP_11 : in STD_LOGIC;
287  RXN_11 : in STD_LOGIC;
288  RXP_12 : in STD_LOGIC;
289  RXN_12 : in STD_LOGIC;
290  RXP_13 : in STD_LOGIC;
291  RXN_13 : in STD_LOGIC;
292  RXP_14 : in STD_LOGIC;
293  RXN_14 : in STD_LOGIC;
294  RXP_15 : in STD_LOGIC;
295  RXN_15 : in STD_LOGIC;
296  RXP_16 : in STD_LOGIC;
297  RXN_16 : in STD_LOGIC;
298  RXP_17 : in STD_LOGIC;
299  RXN_17 : in STD_LOGIC;
300  RXP_18 : in STD_LOGIC;
301  RXN_18 : in STD_LOGIC;
302  RXP_19 : in STD_LOGIC;
303  RXN_19 : in STD_LOGIC;
304  RXP_20 : in STD_LOGIC;
305  RXN_20 : in STD_LOGIC;
306  RXP_21 : in STD_LOGIC;
307  RXN_21 : in STD_LOGIC;
308  RXP_22 : in STD_LOGIC;
309  RXN_22 : in STD_LOGIC;
310  RXP_23 : in STD_LOGIC;
311  RXN_23 : in STD_LOGIC;
312 
313 
314 
315 
316 
317 -- jFEX_RXP : in std_logic;
318 -- jFEX_RXN : in std_logic;
319 
320 
321 
322 
323 
324 
325  ----readout_ctrl specific
326 
327  RO_CTRL_TXN : out std_logic;
328  RO_CTRL_TXP : out std_logic;
329 
330 -- DRP_CLK_IN : in std_logic
331 -- DRP_CLK_IN_P : in std_logic;
332 -- DRP_CLK_IN_N : in std_logic
333 
334  --combined_ttc
335 
336  RXP_ttc : in std_logic;
337  RXN_ttc : in std_logic;
338 
339  CTTC_rxp_alt : in std_logic;
340  CTTC_rxn_alt : in std_logic;
341 
342 
343 
344 --Full Mode Interface
345 
346 
347  --gtrxn_in : in std_logic_vector(3 downto 0);
348  -- gtrxp_in : in std_logic_vector(3 downto 0);
349 
350  -- gttxn_out : out std_logic_vector(3 downto 0);
351  -- gttxp_out : out std_logic_vector(3 downto 0);
352 
353 --first full mode interface (2-channel in quad shared with Aurora)
354  fm1_gttxn_out : out std_logic_vector(1 downto 0);
355  fm1_gttxp_out : out std_logic_vector(1 downto 0);
356 
357 --second full mode interface (2-channel in quad shared with Aurora)
358  fm2_gttxn_out : out std_logic_vector(1 downto 0);
359  fm2_gttxp_out : out std_logic_vector(1 downto 0);
360 
361 
362 
363 -- CLK_40 : in STD_LOGIC
364  ----board tieoff signals
365  CK_PWR_DNB : out std_logic;
366  REF_CLK_SEL : out std_logic;
367  CK_SYNCB : out std_logic;
368  PWR_CON3 : out std_logic;
369  PWR_CON4 : out std_logic
370 -- these are also buried in the GPIO pins and constraints.
371 -- SPI_LE : out std_logic;
372 -- TPOD1_RST : out std_logic;
373 -- TPOD2_RST : out std_logic;
374 -- TPOD3_RST : out std_logic;
375 -- RPOD_RST : out std_logic
376 
377 -- LED3 : out std_logic
378 
379 
380 
381 
382 
383  );
384  end top_rod_jfex;
385 
386 architecture rtl of top_rod_jfex is
387 
388 COMPONENT backplane_control_ila
389  PORT (
390  clk : IN STD_LOGIC;
391  probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
392  );
393 END COMPONENT ;
394 
395 
396 
397 
398  component packet_processor_clock
399  port
400  (-- Clock in ports
401  -- Clock out ports
402  pp_clock : out std_logic;
403  rt_clock : out std_logic;
404  -- Status and control signals
405  locked : out std_logic;
406  clk_in1 : in std_logic
407  );
408  end component;
409 
410 --component jfex_aurora_ila_clock_gen
411 --port
412 -- (-- Clock in ports
413 -- -- Clock out ports
414 -- clk_out1 : out std_logic;
415 -- clk_in1 : in std_logic
416 -- );
417 --end component;
418 
419 
420 
421  component ROD_system
422  generic (
423  GLOBAL_DATE : std_logic_vector(31 downto 0) := x"20201005";
424  GLOBAL_TIME : std_logic_vector(31 downto 0) := x"00000001";
425  GLOBAL_VER : std_logic_vector(31 downto 0) := x"00000002";
426  GLOBAL_SHA : std_logic_vector(31 downto 0) := x"00000003";
427  TOP_VER : std_logic_vector(31 downto 0) := x"00000004";
428  TOP_SHA : std_logic_vector(31 downto 0) := x"00000005";
429  CON_VER : std_logic_vector(31 downto 0) := x"00000006";
430  CON_SHA : std_logic_vector(31 downto 0) := x"00000007";
431  HOG_VER : std_logic_vector(31 downto 0) := x"00000008";
432  HOG_SHA : std_logic_vector(31 downto 0) := x"00000009";
433 
434  --IPBus XML
435  XML_SHA : std_logic_vector(31 downto 0) := x"0000000a";
436  XML_VER : std_logic_vector(31 downto 0) := x"0000000b";
437 
438  ROD_JFEX_SHA : std_logic_vector(31 downto 0) := x"0000000c";
439  ROD_JFEX_VER : std_logic_vector(31 downto 0) := x"0000000d";
440 
441  jfex_rod : integer := 0;
442  efex_rod : integer := 0;
443  golden_rod : integer := 0;
444 
445  -----------------------------------------
446  Module_ID : std_logic_vector (31 downto 0) := x"00000001";
447 -- XmlVersion : std_logic_vector (31 downto 0) := x"00000002";
448  BuildTimeAndDate : std_logic_vector (31 downto 0) := x"00000003";
449  FirmwareVersion : std_logic_vector (31 downto 0) := x"00000004"
450  );
451 
452 
453  port (
454  ipbr_backplane: in ipb_rbus;
455  ipbw_backplane: out ipb_wbus;
456  ipbr_Processor: in ipb_rbus;
457  ipbw_Processor: out ipb_wbus;
458  ipb_clk : out std_logic;
459  ipb_rst : out std_logic;
460  rotary_switch : in std_logic_vector(3 downto 0);
461  CLK_125 : in std_logic;
462  gtx_clk_bufg_out : out std_logic;
463 
464 
465  phy_resetn : out std_logic;
466 
467  -- RGMII Interface
468  ------------------
469  rgmii_txd : out std_logic_vector(3 downto 0);
470  rgmii_tx_ctl : out std_logic;
471  rgmii_txc : out std_logic;
472  rgmii_rxd : in std_logic_vector(3 downto 0);
473  rgmii_rx_ctl : in std_logic;
474  rgmii_rxc : in std_logic;
475 
476  -- MDIO Interface
477  -----------------
478  mdio : inout std_logic;
479  mdc : out std_logic;
480  reset_error : in std_logic;
481 
482  --LEDs
483  -----------------
484  leds : out std_logic_vector(1 downto 0);
485  userled : out std_logic;
486 
487  -- GPIO Interface
488  -------------------
489  gp_button : in std_logic;
490  test1_2 : in std_logic;
491  test1_3 : in std_logic;
492  test1_4 : in std_logic;
493  test1_5 : in std_logic;
494  t_wrn_b : in std_logic;
495  smbalert_b : in std_logic;
496  -- gpio2_tri_i(7) => ,
497  -- gpio2_tri_i(8) => ,
498  ck_pll_lock : in std_logic;
499  ck_int : in std_logic;
500  phy_int : in std_logic;
501  t_pod0_int : in std_logic;
502  t_pod1_int : in std_logic;
503  t_pod2_int : in std_logic;
504  r_pod_int : in std_logic;
505  loc_addr1 : in std_logic;
506  loc_addr2 : in std_logic;
507  loc_addr3 : in std_logic;
508  loc_addr4 : in std_logic;
509  loc_addr5 : in std_logic;
510  loc_addr6 : in std_logic;
511  loc_addr7 : in std_logic;
512  loc_addr8 : in std_logic;
513 
514 -- rod_gp_led : out std_logic;
515  FP_GP_LED_B : out std_logic;
516  FP_RUN_LED_B : out std_logic;
517  lemo : out std_logic;
518  -- gpio_tri_o(4) => ,
519  pwr_con3 : out std_logic;
520  pwr_con4 : out std_logic;
521  -- gpio_tri_o(7) => ,
522  ck_pwr_dnb : out std_logic;
523  ref_clk_sel : out std_logic;
524  ck_syncb : out std_logic;
525 -- phy_rst_n : out std_logic;
526  t_pod0_rst_b : out std_logic;
527  t_pod1_rst_b : out std_logic;
528  t_pod2_rst_b : out std_logic;
529  r_pod_rst_b : out std_logic;
530 
531  --Configuration Flash Interface
532  ---------------------------------
533  EMC_INTF_addr : out STD_LOGIC_VECTOR ( 28 downto 0 );
534  EMC_INTF_ce_n : out STD_LOGIC_VECTOR ( 0 to 0 );
535  EMC_INTF_oen : out STD_LOGIC_VECTOR ( 0 to 0 );
536  EMC_INTF_wen : out STD_LOGIC;
537  emc_intf_dq_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
538 
539  --I2C 1,0 interface
540  ----------------------------------
541  iic_1_scl_io : inout STD_LOGIC;
542  iic_1_sda_io : inout STD_LOGIC;
543  iic_scl_io : inout STD_LOGIC;
544  iic_sda_io : inout STD_LOGIC;
545 
546  --SPI Interface
547  ------------------------------------
548  CK_SPI_MOSI : inout STD_LOGIC; --MOSI
549  CK_SPI_MISO : inout STD_LOGIC; --MISO
550  CK_SPI_CK : inout STD_LOGIC;
551  CK_SPI_LE : inout STD_LOGIC;
552 
553  --XADC interface
554  --------------------------------------
555  Vp_Vn_v_n : in STD_LOGIC;
556  Vp_Vn_v_p : in STD_LOGIC
557 
558 
559 
560  );
561  end component;
562 
563 
564  component jfex_backplane
565  Port (
566 pp_clock : in std_logic;
567 clk_160 : out std_logic;
568 backplane_control : in std_logic_vector(31 downto 0);
569 --cttc_cpllreset_in : in STD_LOGIC;
570  cttc_cpllpd_in : in STD_LOGIC;
571  cttc_rxbufreset_in : in STD_LOGIC;
572  cttc_rxpcsreset_in : in STD_LOGIC;
573  cttc_rxpmareset_in : in STD_LOGIC;
574  cttc_rxcdrhold_in : in STD_LOGIC;
575  cttc_rxpd_in : in STD_LOGIC;
576 
577 
578 GTCLK_q112_c0p : in STD_LOGIC;
579 GTCLK_q112_c0n : in STD_LOGIC;
580 GTCLK_q115_c0p : in STD_LOGIC;
581 GTCLK_q115_c0n : in STD_LOGIC;
582 
583 GTCLK_q118_c0p : in STD_LOGIC;
584 GTCLK_q118_c0n : in STD_LOGIC;
585 
586 GTCLK_q211_c0p : in STD_LOGIC;
587 GTCLK_q211_c0n : in STD_LOGIC;
588 
589 GTCLK_q214_c0p : in STD_LOGIC;
590 GTCLK_q214_c0n : in STD_LOGIC;
591 GTCLK_q217_c0p : in STD_LOGIC;
592 GTCLK_q217_c0n : in STD_LOGIC;
593 
594 
595 --GTCLK_q219_c0p : in std_logic;
596 --GTCLK_q219_c0n : in std_logic;
597 gt_refclk_q219_c0 : in std_logic;
598 
599  vio_chan_reset : in std_logic;
600  rx_GTReset : out std_logic;
601  rx_reset : out std_logic;
602  sys_top_reset : in std_logic;
603 -----aurora slot-4 lane-1 ----------------
604  RXP_0 : in STD_LOGIC;
605  RXN_0 : in STD_LOGIC;
606 
607 
608  CHANNEL_STAT_0 : out std_logic_vector(31 downto 0);
609  CHANNEL_CTRL_0 : in std_logic_vector(31 downto 0);
610  m_axi_rx_tdata_0 : out std_logic_vector(63 downto 0);
611  m_axi_rx_tvalid_0 : out std_logic;
612  m_axi_rx_tlast_0 : out std_logic;
613  -- User Flow Control RX Inteface
614  m_axi_ufc_rx_tdata_0 : out std_logic_vector(31 downto 0);
615  m_axi_ufc_rx_tkeep_0 : out std_logic_vector(7 downto 0);
616  m_axi_ufc_rx_tvalid_0 : out std_logic;
617  m_axi_ufc_rx_tlast_0 : out std_logic;
618 
619  user_clk_out_0 : out std_logic;
620  --user_clk_slot_4 : out std_logic;
621 ------------------------------------------------
622 
623 -----aurora slot-4 lane-2 ----------------
624  RXP_1 : in STD_LOGIC;
625  RXN_1 : in STD_LOGIC;
626 
627  CHANNEL_CTRL_1 : in std_logic_vector(31 downto 0);
628 
629  CHANNEL_STAT_1 : out std_logic_vector(31 downto 0);
630  m_axi_rx_tdata_1 : out std_logic_vector(63 downto 0);
631  --m_axi_rx_tkeep_1 : out std_logic_vector(7 downto 0);
632  m_axi_rx_tvalid_1 : out std_logic;
633  m_axi_rx_tlast_1 : out std_logic;
634  -- User Flow Control RX Inteface
635  m_axi_ufc_rx_tdata_1 : out std_logic_vector(31 downto 0);
636  m_axi_ufc_rx_tkeep_1 : out std_logic_vector(7 downto 0);
637  m_axi_ufc_rx_tvalid_1 : out std_logic;
638  m_axi_ufc_rx_tlast_1 : out std_logic;
639 
640  user_clk_out_1 : out std_logic;
641 ------------------------------------------------
642 -----aurora slot-4 lane-3 ----------------
643  RXP_2 : in STD_LOGIC;
644 RXN_2 : in STD_LOGIC;
645 
646 
647 CHANNEL_CTRL_2 : in std_logic_vector(31 downto 0);
648 CHANNEL_STAT_2 : out std_logic_vector(31 downto 0);
649 m_axi_rx_tdata_2 : out std_logic_vector(63 downto 0);
650 --m_axi_rx_tkeep_2 : out std_logic_vector(7 downto 0);
651 m_axi_rx_tvalid_2 : out std_logic;
652 m_axi_rx_tlast_2 : out std_logic;
653  -- User Flow Control RX Inteface
654 m_axi_ufc_rx_tdata_2 : out std_logic_vector(31 downto 0);
655 m_axi_ufc_rx_tkeep_2 : out std_logic_vector(7 downto 0);
656 m_axi_ufc_rx_tvalid_2 : out std_logic;
657 m_axi_ufc_rx_tlast_2 : out std_logic;
658 
659 user_clk_out_2 : out std_logic;
660 
661 -----aurora slot-4 lane-4 ----------------
662 RXP_3 : in STD_LOGIC;
663 RXN_3 : in STD_LOGIC;
664 
665 
666 CHANNEL_CTRL_3 : in std_logic_vector(31 downto 0);
667 CHANNEL_STAT_3 : out std_logic_vector(31 downto 0);
668 m_axi_rx_tdata_3 : out std_logic_vector(63 downto 0);
669 --m_axi_rx_tkeep_3 : out std_logic_vector(7 downto 0);
670 m_axi_rx_tvalid_3 : out std_logic;
671 m_axi_rx_tlast_3 : out std_logic;
672  -- User Flow Control RX Inteface
673 m_axi_ufc_rx_tdata_3 : out std_logic_vector(31 downto 0);
674 m_axi_ufc_rx_tkeep_3 : out std_logic_vector(7 downto 0);
675 m_axi_ufc_rx_tvalid_3 : out std_logic;
676 m_axi_ufc_rx_tlast_3 : out std_logic;
677 
678 user_clk_out_3 : out std_logic;
679 
680 
681  CLK_125 : in std_logic;
682  GT_RESET_IN : in std_logic;
683  RESET : in std_logic;
684 
685 -----aurora slot-5 lane-1 ----------------
686  RXP_4 : in STD_LOGIC;
687  RXN_4 : in STD_LOGIC;
688 
689 
690  CHANNEL_CTRL_4 : in std_logic_vector(31 downto 0);
691  CHANNEL_STAT_4 : out std_logic_vector(31 downto 0);
692  m_axi_rx_tdata_4 : out std_logic_vector(63 downto 0);
693 -- m_axi_rx_tkeep_4 : out std_logic_vector(7 downto 0);
694  m_axi_rx_tvalid_4 : out std_logic;
695  m_axi_rx_tlast_4 : out std_logic;
696  -- User Flow Control RX Inteface
697  m_axi_ufc_rx_tdata_4 : out std_logic_vector(31 downto 0);
698  m_axi_ufc_rx_tkeep_4 : out std_logic_vector(7 downto 0);
699  m_axi_ufc_rx_tvalid_4 : out std_logic;
700  m_axi_ufc_rx_tlast_4 : out std_logic;
701 
702  user_clk_out_4 : out std_logic;
703  user_clk_slot_5 : out std_logic;
704 ------------------------------------------------
705 
706 -----aurora slot-5 lane-2 ----------------
707  RXP_5 : in STD_LOGIC;
708  RXN_5 : in STD_LOGIC;
709 
710 
711  CHANNEL_CTRL_5 : in std_logic_vector(31 downto 0);
712  CHANNEL_STAT_5 : out std_logic_vector(31 downto 0);
713  m_axi_rx_tdata_5 : out std_logic_vector(63 downto 0);
714  m_axi_rx_tvalid_5 : out std_logic;
715  m_axi_rx_tlast_5 : out std_logic;
716  -- User Flow Control RX Inteface
717  m_axi_ufc_rx_tdata_5 : out std_logic_vector(31 downto 0);
718  m_axi_ufc_rx_tkeep_5 : out std_logic_vector(7 downto 0);
719  m_axi_ufc_rx_tvalid_5 : out std_logic;
720  m_axi_ufc_rx_tlast_5 : out std_logic;
721 
722  user_clk_out_5 : out std_logic;
723 
724 
725 -----aurora slot-5 lane-3 ----------------
726  RXP_6 : in STD_LOGIC;
727  RXN_6 : in STD_LOGIC;
728 
729 
730  CHANNEL_CTRL_6 : in std_logic_vector(31 downto 0);
731  CHANNEL_STAT_6 : out std_logic_vector(31 downto 0);
732  m_axi_rx_tdata_6 : out std_logic_vector(63 downto 0);
733  m_axi_rx_tvalid_6 : out std_logic;
734  m_axi_rx_tlast_6 : out std_logic;
735  -- User Flow Control RX Inteface
736  m_axi_ufc_rx_tdata_6 : out std_logic_vector(31 downto 0);
737  m_axi_ufc_rx_tkeep_6 : out std_logic_vector(7 downto 0);
738  m_axi_ufc_rx_tvalid_6 : out std_logic;
739  m_axi_ufc_rx_tlast_6 : out std_logic;
740 
741  user_clk_out_6 : out std_logic;
742 ------------------------------------------------
743 
744 -----aurora slot-5 lane-4 ----------------
745  RXP_7 : in STD_LOGIC;
746  RXN_7 : in STD_LOGIC;
747 
748  CHANNEL_CTRL_7 : in std_logic_vector(31 downto 0);
749  CHANNEL_STAT_7 : out std_logic_vector(31 downto 0);
750  m_axi_rx_tdata_7 : out std_logic_vector(63 downto 0);
751  m_axi_rx_tvalid_7 : out std_logic;
752  m_axi_rx_tlast_7 : out std_logic;
753  -- User Flow Control RX Inteface
754  m_axi_ufc_rx_tdata_7 : out std_logic_vector(31 downto 0);
755  m_axi_ufc_rx_tkeep_7 : out std_logic_vector(7 downto 0);
756  m_axi_ufc_rx_tvalid_7 : out std_logic;
757  m_axi_ufc_rx_tlast_7 : out std_logic;
758 
759  user_clk_out_7 : out std_logic;
760 ------------------------------------------------
761 
762 -----aurora slot-8 lane-1 ----------------
763  RXP_8 : in STD_LOGIC;
764  RXN_8 : in STD_LOGIC;
765  CHANNEL_CTRL_8 : in std_logic_vector(31 downto 0);
766  CHANNEL_STAT_8 : out std_logic_vector(31 downto 0);
767  m_axi_rx_tdata_8 : out std_logic_vector(63 downto 0);
768  m_axi_rx_tvalid_8 : out std_logic;
769  m_axi_rx_tlast_8 : out std_logic;
770  -- User Flow Control RX Inteface
771  m_axi_ufc_rx_tdata_8 : out std_logic_vector(31 downto 0);
772  m_axi_ufc_rx_tvalid_8 : out std_logic;
773  m_axi_ufc_rx_tlast_8 : out std_logic;
774 
775  user_clk_out_8 : out std_logic;
776 
777 -----aurora slot-8 lane-2 ----------------
778  RXP_9 : in STD_LOGIC;
779  RXN_9 : in STD_LOGIC;
780  CHANNEL_CTRL_9 : in std_logic_vector(31 downto 0);
781  CHANNEL_STAT_9 : out std_logic_vector(31 downto 0);
782  m_axi_rx_tdata_9 : out std_logic_vector(63 downto 0);
783  m_axi_rx_tvalid_9 : out std_logic;
784  m_axi_rx_tlast_9 : out std_logic;
785  -- User Flow Control RX Inteface
786  m_axi_ufc_rx_tdata_9 : out std_logic_vector(31 downto 0);
787  m_axi_ufc_rx_tvalid_9 : out std_logic;
788  m_axi_ufc_rx_tlast_9 : out std_logic;
789 
790  user_clk_out_9 : out std_logic;
791 
792 -----aurora slot-8 lane-3 ----------------
793  RXP_10 : in STD_LOGIC;
794  RXN_10 : in STD_LOGIC;
795  CHANNEL_CTRL_10 : in std_logic_vector(31 downto 0);
796  CHANNEL_STAT_10 : out std_logic_vector(31 downto 0);
797  m_axi_rx_tdata_10 : out std_logic_vector(63 downto 0);
798  m_axi_rx_tvalid_10 : out std_logic;
799  m_axi_rx_tlast_10 : out std_logic;
800  -- User Flow Control RX Inteface
801  m_axi_ufc_rx_tdata_10 : out std_logic_vector(31 downto 0);
802  m_axi_ufc_rx_tvalid_10 : out std_logic;
803  m_axi_ufc_rx_tlast_10 : out std_logic;
804 
805  user_clk_out_10 : out std_logic;
806 
807 
808 -----aurora slot-9 lane-1 ----------------
809  RXP_11 : in STD_LOGIC;
810  RXN_11 : in STD_LOGIC;
811  CHANNEL_CTRL_11 : in std_logic_vector(31 downto 0);
812  CHANNEL_STAT_11 : out std_logic_vector(31 downto 0);
813  m_axi_rx_tdata_11 : out std_logic_vector(63 downto 0);
814  m_axi_rx_tvalid_11 : out std_logic;
815  m_axi_rx_tlast_11 : out std_logic;
816  -- User Flow Control RX Inteface
817  m_axi_ufc_rx_tdata_11 : out std_logic_vector(31 downto 0);
818  m_axi_ufc_rx_tvalid_11 : out std_logic;
819  m_axi_ufc_rx_tlast_11 : out std_logic;
820 
821  user_clk_out_11 : out std_logic;
822 
823 
824 -----------------------------------------------------
825 
826 -----aurora slot-9 lane-1 ----------------
827  RXP_12 : in STD_LOGIC;
828  RXN_12 : in STD_LOGIC;
829  CHANNEL_CTRL_12 : in std_logic_vector(31 downto 0);
830  CHANNEL_STAT_12 : out std_logic_vector(31 downto 0);
831  m_axi_rx_tdata_12 : out std_logic_vector(63 downto 0);
832  m_axi_rx_tvalid_12 : out std_logic;
833  m_axi_rx_tlast_12 : out std_logic;
834  -- User Flow Control RX Inteface
835  m_axi_ufc_rx_tdata_12 : out std_logic_vector(31 downto 0);
836  m_axi_ufc_rx_tvalid_12 : out std_logic;
837  m_axi_ufc_rx_tlast_12 : out std_logic;
838 
839  user_clk_out_12 : out std_logic;
840 
841 -----aurora slot-9 lane-2 ----------------
842 
843  RXP_13 : in STD_LOGIC;
844  RXN_13 : in STD_LOGIC;
845  CHANNEL_CTRL_13 : in std_logic_vector(31 downto 0);
846  CHANNEL_STAT_13 : out std_logic_vector(31 downto 0);
847  m_axi_rx_tdata_13 : out std_logic_vector(63 downto 0);
848  m_axi_rx_tvalid_13 : out std_logic;
849  m_axi_rx_tlast_13 : out std_logic;
850  -- User Flow Control RX Inteface
851  m_axi_ufc_rx_tdata_13 : out std_logic_vector(31 downto 0);
852  m_axi_ufc_rx_tvalid_13 : out std_logic;
853  m_axi_ufc_rx_tlast_13 : out std_logic;
854 
855  user_clk_out_13 : out std_logic;
856 
857 
858 -----aurora slot-9 lane-3 ----------------
859 
860  RXP_14 : in STD_LOGIC;
861  RXN_14 : in STD_LOGIC;
862  CHANNEL_CTRL_14 : in std_logic_vector(31 downto 0);
863  CHANNEL_STAT_14 : out std_logic_vector(31 downto 0);
864  m_axi_rx_tdata_14 : out std_logic_vector(63 downto 0);
865  m_axi_rx_tvalid_14 : out std_logic;
866  m_axi_rx_tlast_14 : out std_logic;
867  -- User Flow Control RX Inteface
868  m_axi_ufc_rx_tdata_14 : out std_logic_vector(31 downto 0);
869  m_axi_ufc_rx_tvalid_14 : out std_logic;
870  m_axi_ufc_rx_tlast_14 : out std_logic;
871 
872  user_clk_out_14 : out std_logic;
873 
874 
875 -----aurora slot-9 lane-4 ----------------
876 
877  RXP_15 : in STD_LOGIC;
878  RXN_15 : in STD_LOGIC;
879  CHANNEL_CTRL_15 : in std_logic_vector(31 downto 0);
880  CHANNEL_STAT_15 : out std_logic_vector(31 downto 0);
881  m_axi_rx_tdata_15 : out std_logic_vector(63 downto 0);
882  m_axi_rx_tvalid_15 : out std_logic;
883  m_axi_rx_tlast_15 : out std_logic;
884  -- User Flow Control RX Inteface
885  m_axi_ufc_rx_tdata_15 : out std_logic_vector(31 downto 0);
886  m_axi_ufc_rx_tvalid_15 : out std_logic;
887  m_axi_ufc_rx_tlast_15 : out std_logic;
888 
889  user_clk_out_15 : out std_logic;
890 
891 
892 -----------chan 16------------------------------------
893 -----aurora slot-12 lane-1 ----------------
894 
895  RXP_16 : in STD_LOGIC;
896  RXN_16 : in STD_LOGIC;
897  CHANNEL_CTRL_16 : in std_logic_vector(31 downto 0);
898  CHANNEL_STAT_16 : out std_logic_vector(31 downto 0);
899  m_axi_rx_tdata_16 : out std_logic_vector(63 downto 0);
900  m_axi_rx_tvalid_16 : out std_logic;
901  m_axi_rx_tlast_16 : out std_logic;
902  -- User Flow Control RX Inteface
903  m_axi_ufc_rx_tdata_16 : out std_logic_vector(31 downto 0);
904  m_axi_ufc_rx_tvalid_16 : out std_logic;
905  m_axi_ufc_rx_tlast_16 : out std_logic;
906 
907  user_clk_out_16 : out std_logic;
908 
909 
910 -----------chan 17------------------------------------
911 -----aurora slot-12 lane-2 ----------------
912 
913  RXP_17 : in STD_LOGIC;
914  RXN_17 : in STD_LOGIC;
915  CHANNEL_CTRL_17 : in std_logic_vector(31 downto 0);
916  CHANNEL_STAT_17 : out std_logic_vector(31 downto 0);
917  m_axi_rx_tdata_17 : out std_logic_vector(63 downto 0);
918  m_axi_rx_tvalid_17 : out std_logic;
919  m_axi_rx_tlast_17 : out std_logic;
920  -- User Flow Control RX Inteface
921  m_axi_ufc_rx_tdata_17 : out std_logic_vector(31 downto 0);
922  m_axi_ufc_rx_tvalid_17 : out std_logic;
923  m_axi_ufc_rx_tlast_17 : out std_logic;
924 
925  user_clk_out_17 : out std_logic;
926 
927 -----------chan 18------------------------------------
928 -----aurora slot-12 lane-3 ----------------
929 
930  RXP_18 : in STD_LOGIC;
931  RXN_18 : in STD_LOGIC;
932  CHANNEL_CTRL_18 : in std_logic_vector(31 downto 0);
933  CHANNEL_STAT_18 : out std_logic_vector(31 downto 0);
934  m_axi_rx_tdata_18 : out std_logic_vector(63 downto 0);
935  m_axi_rx_tvalid_18 : out std_logic;
936  m_axi_rx_tlast_18 : out std_logic;
937  -- User Flow Control RX Inteface
938  m_axi_ufc_rx_tdata_18 : out std_logic_vector(31 downto 0);
939  m_axi_ufc_rx_tvalid_18 : out std_logic;
940  m_axi_ufc_rx_tlast_18 : out std_logic;
941 
942  user_clk_out_18 : out std_logic;
943 
944 -----------chan 19------------------------------------
945 -----aurora slot-12 lane-4 ----------------
946 
947  RXP_19 : in STD_LOGIC;
948  RXN_19 : in STD_LOGIC;
949  CHANNEL_CTRL_19 : in std_logic_vector(31 downto 0);
950  CHANNEL_STAT_19 : out std_logic_vector(31 downto 0);
951  m_axi_rx_tdata_19 : out std_logic_vector(63 downto 0);
952  m_axi_rx_tvalid_19 : out std_logic;
953  m_axi_rx_tlast_19 : out std_logic;
954  -- User Flow Control RX Inteface
955  m_axi_ufc_rx_tdata_19 : out std_logic_vector(31 downto 0);
956  m_axi_ufc_rx_tvalid_19 : out std_logic;
957  m_axi_ufc_rx_tlast_19 : out std_logic;
958 
959  user_clk_out_19 : out std_logic;
960 
961 -----------------------------------------------
962 -----------chan 20------------------------------------
963 -----aurora slot-13 lane-1 ----------------
964 
965  RXP_20 : in STD_LOGIC;
966  RXN_20 : in STD_LOGIC;
967  CHANNEL_CTRL_20 : in std_logic_vector(31 downto 0);
968  CHANNEL_STAT_20 : out std_logic_vector(31 downto 0);
969  m_axi_rx_tdata_20 : out std_logic_vector(63 downto 0);
970  m_axi_rx_tvalid_20 : out std_logic;
971  m_axi_rx_tlast_20 : out std_logic;
972  -- User Flow Control RX Inteface
973  m_axi_ufc_rx_tdata_20 : out std_logic_vector(31 downto 0);
974  m_axi_ufc_rx_tvalid_20 : out std_logic;
975  m_axi_ufc_rx_tlast_20 : out std_logic;
976 
977  user_clk_out_20 : out std_logic;
978 
979 
980 -----------chan 21------------------------------------
981 -----aurora slot-13 lane-2 ----------------
982 
983  RXP_21 : in STD_LOGIC;
984  RXN_21 : in STD_LOGIC;
985  CHANNEL_CTRL_21 : in std_logic_vector(31 downto 0);
986  CHANNEL_STAT_21 : out std_logic_vector(31 downto 0);
987  m_axi_rx_tdata_21 : out std_logic_vector(63 downto 0);
988  m_axi_rx_tvalid_21 : out std_logic;
989  m_axi_rx_tlast_21 : out std_logic;
990  -- User Flow Control RX Inteface
991  m_axi_ufc_rx_tdata_21 : out std_logic_vector(31 downto 0);
992  m_axi_ufc_rx_tvalid_21 : out std_logic;
993  m_axi_ufc_rx_tlast_21 : out std_logic;
994 
995  user_clk_out_21 : out std_logic;
996 
997 -----------chan 22------------------------------------
998 -----aurora slot-13 lane-3 ----------------
999 
1000 
1001  RXP_22 : in STD_LOGIC;
1002  RXN_22 : in STD_LOGIC;
1003  CHANNEL_CTRL_22 : in std_logic_vector(31 downto 0);
1004  CHANNEL_STAT_22 : out std_logic_vector(31 downto 0);
1005  m_axi_rx_tdata_22 : out std_logic_vector(63 downto 0);
1006  m_axi_rx_tvalid_22 : out std_logic;
1007  m_axi_rx_tlast_22 : out std_logic;
1008  -- User Flow Control RX Inteface
1009  m_axi_ufc_rx_tdata_22 : out std_logic_vector(31 downto 0);
1010  m_axi_ufc_rx_tvalid_22 : out std_logic;
1011  m_axi_ufc_rx_tlast_22 : out std_logic;
1012 
1013  user_clk_out_22 : out std_logic;
1014 
1015 -----------chan 23------------------------------------
1016 -----aurora slot-13 lane-4 ----------------
1017  RXP_23 : in STD_LOGIC;
1018  RXN_23 : in STD_LOGIC;
1019  CHANNEL_CTRL_23 : in std_logic_vector(31 downto 0);
1020  CHANNEL_STAT_23 : out std_logic_vector(31 downto 0);
1021  m_axi_rx_tdata_23 : out std_logic_vector(63 downto 0);
1022  m_axi_rx_tvalid_23 : out std_logic;
1023  m_axi_rx_tlast_23 : out std_logic;
1024  -- User Flow Control RX Inteface
1025  m_axi_ufc_rx_tdata_23 : out std_logic_vector(31 downto 0);
1026  m_axi_ufc_rx_tvalid_23 : out std_logic;
1027  m_axi_ufc_rx_tlast_23 : out std_logic;
1028 
1029  user_clk_out_23 : out std_logic;
1030 
1031 -----------------------------------------------------------------------------
1032 
1033 
1034 
1035 
1036 
1037 ----readout_ctrl specific
1038  ro_user_clock : out STD_LOGIC;
1039  ro_controller_reset : out STD_LOGIC;
1040  ro_txcharisk : in std_logic_vector(3 downto 0);
1041  ro_txdata : in std_logic_vector(31 downto 0);
1042  ro_status : out std_logic_vector(7 downto 0);
1043 
1044  RO_CTRL_TXN : out std_logic;
1045  RO_CTRL_TXP : out std_logic;
1046 
1047  DRP_CLK_IN : in std_logic;
1048  MASTER_RESET : out std_logic;
1049  SW2 : in std_logic;
1050 
1051 
1052 --combined_TTC
1053 
1054  ttc_RXP : in std_logic;
1055  ttc_RXN : in std_logic;
1056  ttc_word_0 : out std_logic_vector(31 downto 0);
1057  ttc_word_1 : out std_logic_vector(31 downto 0);
1058  ttc_word_2 : out std_logic_vector(31 downto 0);
1059  ttc_word_3 : out std_logic_vector(31 downto 0);
1060  ttc_seq : out std_logic_vector(1 downto 0);
1061  cttc_usrclk : out std_logic;
1062  ttc_reset : in std_logic;
1063  ttc_status : out std_logic_vector(31 downto 0);
1064 
1065  --------------------------ttc MGT ports -----------------------------
1066  BP_CTTC_rxdata : out std_logic_vector (31 downto 0);
1067  BP_CTTC_rxcharisk : out std_logic_vector (3 downto 0);
1068  BP_CTTC_MGT_bus : out STD_LOGIC_VECTOR(31 DOWNTO 0);
1069  BP_CTTC_rxoutclk : out std_logic
1070 
1071 
1072  );
1073 end component;
1074 
1075 COMPONENT axi_ch0
1076 
1077 PORT (
1078  clk : IN STD_LOGIC;
1079 
1080  probe0 : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
1081  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1082  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1083  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1084  probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
1085 );
1086 END COMPONENT ;
1087 
1088 component fex_rx_checker
1089  Port ( clock : in STD_LOGIC;
1090  reset : in STD_LOGIC;
1091  tvalid : in STD_LOGIC;
1092  tlast : in STD_LOGIC;
1093  tdata : in STD_logic_vector(63 downto 0);
1094  channel_up : in STD_LOGIC;
1095  soft_error : in STD_LOGIC;
1096  hard_error : in STD_LOGIC;
1097  L1A : in STD_LOGIC;
1098  l1id_mis_stretch : in std_logic
1099  );
1100 end component;
1101 
1102 
1103 
1104 
1105  component packet_processor
1106  generic (
1107  jfex : integer := 1;
1108  sim : integer := 0;
1109  CRC20_G_Poly : std_logic_vector(19 downto 0) := x"8349f"; --old poly
1110  -- Width of register file S_AXI data bus
1111  C_S_AXI_DATA_WIDTH : integer := 32;
1112  -- Width of register file S_AXI address bus
1113  C_S_AXI_ADDR_WIDTH : integer := 9;
1114  --width of Aurora AXI output
1115  bp_width : integer := 64
1116  );
1117  Port (
1118  ipb_clk : in STD_LOGIC;
1119  ipb_rst : in STD_LOGIC;
1120 -- ipb_in : in ipb_wbus;
1121 -- ipb_out : out ipb_rbus;
1122 
1123  ipb_in_backplane : in ipb_wbus;
1124  ipb_out_backplane : out ipb_rbus;
1125  ipb_in_processor : in ipb_wbus;
1126  ipb_out_processor : out ipb_rbus;
1127 
1128  geo_location : in STD_LOGIC_VECTOR (7 downto 0);
1129  L1A : out std_logic;
1130  L1A_delay_out : out std_logic;
1131  l1id_mis_stretch : out std_logic;
1132 
1133  full_mode_stat_tob_0 : in std_logic_vector(31 downto 0);
1134  full_mode_stat_bulk_0 : in std_logic_vector(31 downto 0);
1135  full_mode_stat_bulk_1 : in std_logic_vector(31 downto 0);
1136  full_mode_stat_bulk_2 : in std_logic_vector(31 downto 0);
1137  FM_L1id_stat_tob_0 : in std_logic_vector(31 downto 0);
1138  FM_L1id_stat_bulk_0 : in std_logic_vector(31 downto 0);
1139  FM_L1id_stat_bulk_1 : in std_logic_vector(31 downto 0);
1140  FM_L1id_stat_bulk_2 : in std_logic_vector(31 downto 0);
1141 
1142  full_mode_ctrl_tob_0 : out std_logic_vector(31 downto 0);
1143  full_mode_ctrl_bulk_0 : out std_logic_vector(31 downto 0);
1144  full_mode_ctrl_bulk_1 : out std_logic_vector(31 downto 0);
1145  full_mode_ctrl_bulk_2 : out std_logic_vector(31 downto 0);
1146 
1147  stage_fifo_level_tob_0 : in std_logic_vector(15 downto 0);
1148  stage_fifo_level_bulk_0 : in std_logic_vector(15 downto 0);
1149  stage_fifo_level_bulk_1 : in std_logic_vector(15 downto 0);
1150  stage_fifo_level_bulk_2 : in std_logic_vector(15 downto 0);
1151 
1152 
1153  stage_fifo_busy_tob_0 : out STD_LOGIC;
1154  stage_fifo_busy_bulk_0 : out STD_LOGIC;
1155  stage_fifo_busy_bulk_1 : out STD_LOGIC;
1156  stage_fifo_busy_bulk_2 : out STD_LOGIC;
1157  stage_fifo_xoff_tob_0 : out STD_LOGIC;
1158  stage_fifo_xoff_bulk_0 : out STD_LOGIC;
1159  stage_fifo_xoff_bulk_1 : out STD_LOGIC;
1160  stage_fifo_xoff_bulk_2 : out STD_LOGIC;
1161  stage_fifo_full_tob_0 : in STD_LOGIC;
1162  stage_fifo_full_bulk_0 : in STD_LOGIC;
1163  stage_fifo_full_bulk_1 : in STD_LOGIC;
1164  stage_fifo_full_bulk_2 : in STD_LOGIC;
1165 
1166  flx_backpressure_tob_0 : out STD_LOGIC;
1167  flx_backpressure_bulk_0 : out STD_LOGIC;
1168  flx_backpressure_bulk_1 : out STD_LOGIC;
1169  flx_backpressure_bulk_2 : out STD_LOGIC;
1170 
1171 
1172 
1173  pp_clock : in STD_LOGIC;
1174  clk_40 : in std_logic;
1175  clk_160 : in std_logic;
1176  rt_clk : in std_logic;
1177  backplane_control : out std_logic_vector(31 downto 0);
1178  init_clk : in std_logic;
1179  master_reset : in std_logic;
1180  rod_slot : in std_logic;
1181  ck_pll_lock : in std_logic;
1182 
1183  CK_INT : in STD_LOGIC;
1184  SMBALERT_B : in STD_LOGIC;
1185  T_WRN_B : in STD_LOGIC;
1186 -- clk_125 : in STD_LOGIC;
1187  System_RESET : in STD_LOGIC;
1188  flx_backpressure : out std_logic_vector(11 downto 0);
1189 
1190 -- readout_controller ---
1191  ro_user_clock : in STD_LOGIC;
1192  ro_controller_reset : in STD_LOGIC;
1193  ro_txcharisk : out std_logic_vector(3 downto 0);
1194  ro_txdata : out std_logic_vector(31 downto 0);
1195  ro_status : in std_logic_vector(7 downto 0);
1196 
1197 
1198 -- clk_40 : in STD_LOGIC;
1199  aurora_user_clock_0 : in STD_LOGIC;
1200  aurora_user_clock_1 : in STD_LOGIC;
1201  aurora_user_clock_2 : in STD_LOGIC;
1202  aurora_user_clock_3 : in STD_LOGIC;
1203  aurora_user_clock_4 : in STD_LOGIC;
1204  aurora_user_clock_5 : in STD_LOGIC;
1205  aurora_user_clock_6 : in STD_LOGIC;
1206  aurora_user_clock_7 : in STD_LOGIC;
1207  aurora_user_clock_8 : in STD_LOGIC;
1208  aurora_user_clock_9 : in STD_LOGIC;
1209  aurora_user_clock_10 : in STD_LOGIC;
1210  aurora_user_clock_11 : in STD_LOGIC;
1211 
1212  aurora_user_clock_12 : in STD_LOGIC;
1213  aurora_user_clock_13 : in STD_LOGIC;
1214  aurora_user_clock_14 : in STD_LOGIC;
1215  aurora_user_clock_15 : in STD_LOGIC;
1216  aurora_user_clock_16 : in STD_LOGIC;
1217  aurora_user_clock_17 : in STD_LOGIC;
1218  aurora_user_clock_18 : in STD_LOGIC;
1219  aurora_user_clock_19 : in STD_LOGIC;
1220  aurora_user_clock_20 : in STD_LOGIC;
1221  aurora_user_clock_21 : in STD_LOGIC;
1222  aurora_user_clock_22 : in STD_LOGIC;
1223  aurora_user_clock_23 : in STD_LOGIC;
1224 
1225 
1226 
1227  aurora_chan_stat_0 : in STD_LOGIC_VECTOR (31 downto 0);
1228  aurora_chan_stat_1 : in STD_LOGIC_VECTOR (31 downto 0);
1229  aurora_chan_stat_2 : in STD_LOGIC_VECTOR (31 downto 0);
1230  aurora_chan_stat_3 : in STD_LOGIC_VECTOR (31 downto 0);
1231  aurora_chan_stat_4 : in STD_LOGIC_VECTOR (31 downto 0);
1232  aurora_chan_stat_5 : in STD_LOGIC_VECTOR (31 downto 0);
1233  aurora_chan_stat_6 : in STD_LOGIC_VECTOR (31 downto 0);
1234  aurora_chan_stat_7 : in STD_LOGIC_VECTOR (31 downto 0);
1235  aurora_chan_stat_8 : in STD_LOGIC_VECTOR (31 downto 0);
1236  aurora_chan_stat_9 : in STD_LOGIC_VECTOR (31 downto 0);
1237  aurora_chan_stat_10 : in STD_LOGIC_VECTOR (31 downto 0);
1238  aurora_chan_stat_11 : in STD_LOGIC_VECTOR (31 downto 0);
1239  aurora_chan_stat_12 : in STD_LOGIC_VECTOR (31 downto 0);
1240  aurora_chan_stat_13 : in STD_LOGIC_VECTOR (31 downto 0);
1241  aurora_chan_stat_14 : in STD_LOGIC_VECTOR (31 downto 0);
1242  aurora_chan_stat_15 : in STD_LOGIC_VECTOR (31 downto 0);
1243  aurora_chan_stat_16 : in STD_LOGIC_VECTOR (31 downto 0);
1244  aurora_chan_stat_17 : in STD_LOGIC_VECTOR (31 downto 0);
1245  aurora_chan_stat_18 : in STD_LOGIC_VECTOR (31 downto 0);
1246  aurora_chan_stat_19 : in STD_LOGIC_VECTOR (31 downto 0);
1247  aurora_chan_stat_20 : in STD_LOGIC_VECTOR (31 downto 0);
1248  aurora_chan_stat_21 : in STD_LOGIC_VECTOR (31 downto 0);
1249  aurora_chan_stat_22 : in STD_LOGIC_VECTOR (31 downto 0);
1250  aurora_chan_stat_23 : in STD_LOGIC_VECTOR (31 downto 0);
1251 
1252  aurora_chan_control_0 : out STD_LOGIC_VECTOR (31 downto 0);
1253  aurora_chan_control_1 : out STD_LOGIC_VECTOR (31 downto 0);
1254  aurora_chan_control_2 : out STD_LOGIC_VECTOR (31 downto 0);
1255  aurora_chan_control_3 : out STD_LOGIC_VECTOR (31 downto 0);
1256  aurora_chan_control_4 : out STD_LOGIC_VECTOR (31 downto 0);
1257  aurora_chan_control_5 : out STD_LOGIC_VECTOR (31 downto 0);
1258  aurora_chan_control_6 : out STD_LOGIC_VECTOR (31 downto 0);
1259  aurora_chan_control_7 : out STD_LOGIC_VECTOR (31 downto 0);
1260  aurora_chan_control_8 : out STD_LOGIC_VECTOR (31 downto 0);
1261  aurora_chan_control_9 : out STD_LOGIC_VECTOR (31 downto 0);
1262  aurora_chan_control_10 : out STD_LOGIC_VECTOR (31 downto 0);
1263  aurora_chan_control_11 : out STD_LOGIC_VECTOR (31 downto 0);
1264  aurora_chan_control_12 : out STD_LOGIC_VECTOR (31 downto 0);
1265  aurora_chan_control_13 : out STD_LOGIC_VECTOR (31 downto 0);
1266  aurora_chan_control_14 : out STD_LOGIC_VECTOR (31 downto 0);
1267  aurora_chan_control_15 : out STD_LOGIC_VECTOR (31 downto 0);
1268  aurora_chan_control_16 : out STD_LOGIC_VECTOR (31 downto 0);
1269  aurora_chan_control_17 : out STD_LOGIC_VECTOR (31 downto 0);
1270  aurora_chan_control_18 : out STD_LOGIC_VECTOR (31 downto 0);
1271  aurora_chan_control_19 : out STD_LOGIC_VECTOR (31 downto 0);
1272  aurora_chan_control_20 : out STD_LOGIC_VECTOR (31 downto 0);
1273  aurora_chan_control_21 : out STD_LOGIC_VECTOR (31 downto 0);
1274  aurora_chan_control_22 : out STD_LOGIC_VECTOR (31 downto 0);
1275  aurora_chan_control_23 : out STD_LOGIC_VECTOR (31 downto 0);
1276 
1277 
1278 
1279  bp_data_0 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1280  bp_data_1 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1281  bp_data_2 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1282  bp_data_3 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1283  bp_data_4 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1284  bp_data_5 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1285  bp_data_6 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1286  bp_data_7 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1287  bp_data_8 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1288  bp_data_9 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1289  bp_data_10 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1290  bp_data_11 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1291  bp_data_12 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1292  bp_data_13 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1293  bp_data_14 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1294  bp_data_15 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1295  bp_data_16 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1296  bp_data_17 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1297  bp_data_18 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1298  bp_data_19 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1299  bp_data_20 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1300  bp_data_21 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1301  bp_data_22 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1302  bp_data_23 : in STD_LOGIC_VECTOR (bp_width-1 downto 0);
1303 
1304 
1305 
1306 
1307  s_axis_tvalid_0 : in std_logic;
1308  s_axis_tvalid_1 : in std_logic;
1309  s_axis_tvalid_2 : in std_logic;
1310  s_axis_tvalid_3 : in std_logic;
1311  s_axis_tvalid_4 : in std_logic;
1312  s_axis_tvalid_5 : in std_logic;
1313  s_axis_tvalid_6 : in std_logic;
1314  s_axis_tvalid_7 : in std_logic;
1315  s_axis_tvalid_8 : in std_logic;
1316  s_axis_tvalid_9 : in std_logic;
1317  s_axis_tvalid_10 : in std_logic;
1318  s_axis_tvalid_11 : in std_logic;
1319  s_axis_tvalid_12 : in std_logic;
1320  s_axis_tvalid_13 : in std_logic;
1321  s_axis_tvalid_14 : in std_logic;
1322  s_axis_tvalid_15 : in std_logic;
1323  s_axis_tvalid_16 : in std_logic;
1324  s_axis_tvalid_17 : in std_logic;
1325  s_axis_tvalid_18 : in std_logic;
1326  s_axis_tvalid_19 : in std_logic;
1327  s_axis_tvalid_20 : in std_logic;
1328  s_axis_tvalid_21 : in std_logic;
1329  s_axis_tvalid_22 : in std_logic;
1330  s_axis_tvalid_23 : in std_logic;
1331 
1332  s_axis_tlast_0 : in std_logic;
1333  s_axis_tlast_1 : in std_logic;
1334  s_axis_tlast_2 : in std_logic;
1335  s_axis_tlast_3 : in std_logic;
1336  s_axis_tlast_4 : in std_logic;
1337  s_axis_tlast_5 : in std_logic;
1338  s_axis_tlast_6 : in std_logic;
1339  s_axis_tlast_7 : in std_logic;
1340  s_axis_tlast_8 : in std_logic;
1341  s_axis_tlast_9 : in std_logic;
1342  s_axis_tlast_10 : in std_logic;
1343  s_axis_tlast_11 : in std_logic;
1344  s_axis_tlast_12 : in std_logic;
1345  s_axis_tlast_13 : in std_logic;
1346  s_axis_tlast_14 : in std_logic;
1347  s_axis_tlast_15 : in std_logic;
1348  s_axis_tlast_16 : in std_logic;
1349  s_axis_tlast_17 : in std_logic;
1350  s_axis_tlast_18 : in std_logic;
1351  s_axis_tlast_19 : in std_logic;
1352  s_axis_tlast_20 : in std_logic;
1353  s_axis_tlast_21 : in std_logic;
1354  s_axis_tlast_22 : in std_logic;
1355  s_axis_tlast_23 : in std_logic;
1356 
1357 
1358 
1359 
1360 -----the following tready signals can not affect Aurora behaviour, but will instead be used to capture an error condition (input pause needed)
1361  s_axis_tready_0 : out std_logic;
1362  s_axis_tready_1 : out std_logic;
1363  s_axis_tready_2 : out std_logic;
1364  s_axis_tready_3 : out std_logic;
1365  s_axis_tready_4 : out std_logic;
1366  s_axis_tready_5 : out std_logic;
1367  s_axis_tready_6 : out std_logic;
1368  s_axis_tready_7 : out std_logic;
1369  s_axis_tready_8 : out std_logic;
1370  s_axis_tready_9 : out std_logic;
1371  s_axis_tready_10 : out std_logic;
1372  s_axis_tready_11 : out std_logic;
1373  s_axis_tready_12 : out std_logic;
1374  s_axis_tready_13 : out std_logic;
1375  s_axis_tready_14 : out std_logic;
1376  s_axis_tready_15 : out std_logic;
1377  s_axis_tready_16 : out std_logic;
1378  s_axis_tready_17 : out std_logic;
1379  s_axis_tready_18 : out std_logic;
1380  s_axis_tready_19 : out std_logic;
1381  s_axis_tready_20 : out std_logic;
1382  s_axis_tready_21 : out std_logic;
1383  s_axis_tready_22 : out std_logic;
1384  s_axis_tready_23 : out std_logic;
1385 
1386 
1387  s_axi_ufc_rx_tdata_0 : in std_logic_vector(63 downto 0);
1388  s_axi_ufc_rx_tdata_1 : in std_logic_vector(63 downto 0);
1389  s_axi_ufc_rx_tdata_2 : in std_logic_vector(63 downto 0);
1390  s_axi_ufc_rx_tdata_3 : in std_logic_vector(63 downto 0);
1391  s_axi_ufc_rx_tdata_4 : in std_logic_vector(63 downto 0);
1392  s_axi_ufc_rx_tdata_5 : in std_logic_vector(63 downto 0);
1393  s_axi_ufc_rx_tdata_6 : in std_logic_vector(63 downto 0);
1394  s_axi_ufc_rx_tdata_7 : in std_logic_vector(63 downto 0);
1395  s_axi_ufc_rx_tdata_8 : in std_logic_vector(63 downto 0);
1396  s_axi_ufc_rx_tdata_9 : in std_logic_vector(63 downto 0);
1397  s_axi_ufc_rx_tdata_10 : in std_logic_vector(63 downto 0);
1398  s_axi_ufc_rx_tdata_11 : in std_logic_vector(63 downto 0);
1399  s_axi_ufc_rx_tdata_12 : in std_logic_vector(63 downto 0);
1400  s_axi_ufc_rx_tdata_13 : in std_logic_vector(63 downto 0);
1401  s_axi_ufc_rx_tdata_14 : in std_logic_vector(63 downto 0);
1402  s_axi_ufc_rx_tdata_15 : in std_logic_vector(63 downto 0);
1403  s_axi_ufc_rx_tdata_16 : in std_logic_vector(63 downto 0);
1404  s_axi_ufc_rx_tdata_17 : in std_logic_vector(63 downto 0);
1405  s_axi_ufc_rx_tdata_18 : in std_logic_vector(63 downto 0);
1406  s_axi_ufc_rx_tdata_19 : in std_logic_vector(63 downto 0);
1407  s_axi_ufc_rx_tdata_20 : in std_logic_vector(63 downto 0);
1408  s_axi_ufc_rx_tdata_21 : in std_logic_vector(63 downto 0);
1409  s_axi_ufc_rx_tdata_22 : in std_logic_vector(63 downto 0);
1410  s_axi_ufc_rx_tdata_23 : in std_logic_vector(63 downto 0);
1411 
1412  s_axi_ufc_rx_tvalid_0 : in std_logic;
1413  s_axi_ufc_rx_tvalid_1 : in std_logic;
1414  s_axi_ufc_rx_tvalid_2 : in std_logic;
1415  s_axi_ufc_rx_tvalid_3 : in std_logic;
1416  s_axi_ufc_rx_tvalid_4 : in std_logic;
1417  s_axi_ufc_rx_tvalid_5 : in std_logic;
1418  s_axi_ufc_rx_tvalid_6 : in std_logic;
1419  s_axi_ufc_rx_tvalid_7 : in std_logic;
1420  s_axi_ufc_rx_tvalid_8 : in std_logic;
1421  s_axi_ufc_rx_tvalid_9 : in std_logic;
1422  s_axi_ufc_rx_tvalid_10 : in std_logic;
1423  s_axi_ufc_rx_tvalid_11 : in std_logic;
1424  s_axi_ufc_rx_tvalid_12 : in std_logic;
1425  s_axi_ufc_rx_tvalid_13 : in std_logic;
1426  s_axi_ufc_rx_tvalid_14 : in std_logic;
1427  s_axi_ufc_rx_tvalid_15 : in std_logic;
1428  s_axi_ufc_rx_tvalid_16 : in std_logic;
1429  s_axi_ufc_rx_tvalid_17 : in std_logic;
1430  s_axi_ufc_rx_tvalid_18 : in std_logic;
1431  s_axi_ufc_rx_tvalid_19 : in std_logic;
1432  s_axi_ufc_rx_tvalid_20 : in std_logic;
1433  s_axi_ufc_rx_tvalid_21 : in std_logic;
1434  s_axi_ufc_rx_tvalid_22 : in std_logic;
1435  s_axi_ufc_rx_tvalid_23 : in std_logic;
1436 
1437  s_axi_ufc_rx_tlast_0 : in std_logic;
1438  s_axi_ufc_rx_tlast_1 : in std_logic;
1439  s_axi_ufc_rx_tlast_2 : in std_logic;
1440  s_axi_ufc_rx_tlast_3 : in std_logic;
1441  s_axi_ufc_rx_tlast_4 : in std_logic;
1442  s_axi_ufc_rx_tlast_5 : in std_logic;
1443  s_axi_ufc_rx_tlast_6 : in std_logic;
1444  s_axi_ufc_rx_tlast_7 : in std_logic;
1445  s_axi_ufc_rx_tlast_8 : in std_logic;
1446  s_axi_ufc_rx_tlast_9 : in std_logic;
1447  s_axi_ufc_rx_tlast_10 : in std_logic;
1448  s_axi_ufc_rx_tlast_11 : in std_logic;
1449  s_axi_ufc_rx_tlast_12 : in std_logic;
1450  s_axi_ufc_rx_tlast_13 : in std_logic;
1451  s_axi_ufc_rx_tlast_14 : in std_logic;
1452  s_axi_ufc_rx_tlast_15 : in std_logic;
1453  s_axi_ufc_rx_tlast_16 : in std_logic;
1454  s_axi_ufc_rx_tlast_17 : in std_logic;
1455  s_axi_ufc_rx_tlast_18 : in std_logic;
1456  s_axi_ufc_rx_tlast_19 : in std_logic;
1457  s_axi_ufc_rx_tlast_20 : in std_logic;
1458  s_axi_ufc_rx_tlast_21 : in std_logic;
1459  s_axi_ufc_rx_tlast_22 : in std_logic;
1460  s_axi_ufc_rx_tlast_23 : in std_logic;
1461 
1462  multichannel_busy : out std_logic;
1463  combined_busy : in std_logic;
1464 
1465 
1466  channel_enable_vio : in std_logic_vector (23 downto 0);
1467  first_chan_vio : in std_logic_vector (4 downto 0);
1468  last_chan_vio : in std_logic_vector (4 downto 0);
1469  TTC_ignore_vio : in std_logic;
1470  debug_ctrl_vio : in std_logic;
1471 
1472 --- output queue(s)
1473 
1474  m_tvalid_0 : out STD_LOGIC;
1475  m_tlast_0 : out STD_LOGIC;
1476  m_tdata_0 : out STD_LOGIC_VECTOR ((bp_width-1) downto 0);
1477  m_header_marker_0 : out STD_LOGIC;
1478  m_tail_marker_0 : out STD_LOGIC;
1479  m_tready_0 : in STD_LOGIC;
1480 
1481 
1482  bulk_m_tvalid_0 : out STD_LOGIC;
1483  bulk_m_tlast_0 : out STD_LOGIC;
1484  bulk_m_tdata_0 : out STD_LOGIC_VECTOR (63 downto 0);
1485  bulk_m_header_marker_0 : out STD_LOGIC;
1486  bulk_m_tail_marker_0 : out STD_LOGIC;
1487  bulk_m_tready_0 : in STD_LOGIC;
1488 
1489  bulk_m_tvalid_1 : out STD_LOGIC;
1490  bulk_m_tlast_1 : out STD_LOGIC;
1491  bulk_m_tdata_1 : out STD_LOGIC_VECTOR (63 downto 0);
1492  bulk_m_header_marker_1 : out STD_LOGIC;
1493  bulk_m_tail_marker_1 : out STD_LOGIC;
1494  bulk_m_tready_1 : in STD_LOGIC;
1495 
1496  bulk_m_tvalid_2 : out STD_LOGIC;
1497  bulk_m_tlast_2 : out STD_LOGIC;
1498  bulk_m_tdata_2 : out STD_LOGIC_VECTOR (63 downto 0);
1499  bulk_m_header_marker_2 : out STD_LOGIC;
1500  bulk_m_tail_marker_2 : out STD_LOGIC;
1501  bulk_m_tready_2 : in STD_LOGIC;
1502 
1503 --TTC signals
1504  cttc_user_clk : in std_logic;
1505  ttc_status : in std_logic_vector(31 downto 0);
1506  ttc_reset : out std_logic;
1507  hub_link_reset : out std_logic;
1508  ttc_seq : in std_logic_vector(1 downto 0);
1509  ttc_word_0 : in std_logic_vector(31 downto 0);
1510  ttc_word_1 : in std_logic_vector(31 downto 0);
1511  ttc_word_2 : in std_logic_vector(31 downto 0);
1512  ttc_word_3 : in std_logic_vector(31 downto 0);
1513 
1514 
1515  ttc_mux_ctrl : in std_logic;
1516  BP_CTTC_rxdata : in std_logic_vector (31 downto 0);
1517  FM_CTTC_rxdata : in std_logic_vector (31 downto 0);
1518  BP_CTTC_rxcharisk : in std_logic_vector (3 downto 0);
1519  FM_CTTC_rxcharisk : in std_logic_vector (3 downto 0);
1520  BP_CTTC_MGT_bus : in STD_LOGIC_VECTOR(31 DOWNTO 0);
1521  FM_CTTC_MGT_bus : in STD_LOGIC_VECTOR(31 DOWNTO 0);
1522  BP_CTTC_rxoutclk : in STD_LOGIC;
1523  FM_CTTC_rxoutclk : in STD_LOGIC
1524  );
1525 
1526 
1527  end component;
1528 
1529  component system_top_reset
1530  generic (
1531  max_count : std_logic_vector := x"0FFFFFFF"
1532  );
1533  port (
1534  clk40 : in STD_LOGIC;
1535  rod_button : in STD_LOGIC;
1536  sys_top_reset : out STD_LOGIC;
1537  sys_top_reset_b : out STD_LOGIC
1538 
1539  );
1540  end component;
1541 
1542  component reset_count is
1543  generic
1544  (
1545  COUNTER_WIDTH : integer := 5
1546  );
1547 
1548  Port (
1549  clock : in STD_LOGIC;
1550  power_down_b: out STD_LOGIC
1551  );
1552  end component;
1553 
1554 
1555 
1556 
1557 
1558  component IBUF
1559  port (
1560  O : out std_ulogic;
1561  I : in std_ulogic);
1562 
1563  end component;
1564 
1565 
1566 
1567 COMPONENT pp_ctrl_vio
1568  PORT (
1569  clk : IN STD_LOGIC;
1570  probe_out0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
1571  probe_out1 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
1572  probe_out2 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
1573  probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1574  probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1575  probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
1576  );
1577 END COMPONENT;
1578 
1579 
1580 
1581 
1582 
1583 component FM_ROD is
1584  generic(
1585  GTX_TRANSCEIVERS : boolean := false; -- true for GTX, false for GTH
1586  NUM_LINKS : integer := 4;
1587  RECOVER_CLK_FROM_RX_GBT : boolean := false);
1588  port (
1589  GTREFCLK0_N_IN : in std_logic;
1590  GTREFCLK0_P_IN : in std_logic;
1591  RESET_BUTTON : in std_logic;
1592 
1593  --disabling these inputs to use in stand-alone mode
1594  --add them again when integrating into rod top
1595  --temp FM_tx_data : in std_logic_vector(31 downto 0);
1596  --temp FM_tx_dvalid : in std_logic;
1597 
1598 
1599 
1600  app_clk_in : in std_logic;
1601  gtrxn_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1602  gtrxp_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1603  gttxn_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1604  gttxp_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1605 
1606  s_axis_tvalid : in std_logic;
1607  s_axis_tlast : in std_logic;
1608  s_axis_tready : out std_logic;
1609  s_axis_tdata : in std_logic_vector(31 downto 0);
1610  TXOUTCLK_0 : out std_logic;
1611  channel_reset : in std_logic;
1612  TestMode : in std_logic;
1613  interface_reset : out std_logic
1614 
1615 
1616  );
1617  end component;
1618 
1619 component Full_Mode_Tx is
1620 
1621  generic(
1622  DEBUG : integer := 1;
1623  GTX_TRANSCEIVERS : boolean := false; -- true for GTX, false for GTH
1624  NUM_LINKS : integer := 2;
1625  RECOVER_CLK_FROM_RX_GBT : boolean := false);
1626 port (
1627 -- GTREFCLK0_N_IN : in std_logic;
1628 -- GTREFCLK0_P_IN : in std_logic;
1629  GTREFCLK0 : in std_logic;
1630  pp_clock : in std_logic;
1631  RESET_BUTTON : in std_logic;
1632 
1633 
1634  app_clk_in : in std_logic;
1635  gtrxn_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1636  gtrxp_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1637  gttxn_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1638  gttxp_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1639 
1640 
1641 
1642  s_axis_tvalid_0 : in std_logic;
1643  s_axis_tlast_0 : in std_logic;
1644  s_axis_tready_0 : out std_logic;
1645  flx_bp_240_0 : in std_logic;
1646  s_axis_tdata_0 : in std_logic_vector(31 downto 0);
1647  TXOUTCLK_0 : out std_logic;
1648  channel_reset_0 : in std_logic;
1649  soft_reset_0 : in std_logic;
1650  busy_0 : in std_logic;
1651  interface_reset_0 : out std_logic;
1652 
1653  s_axis_tvalid_1 : in std_logic;
1654  s_axis_tlast_1 : in std_logic;
1655  s_axis_tready_1 : out std_logic;
1656  flx_bp_240_1 : in std_logic;
1657  s_axis_tdata_1 : in std_logic_vector(31 downto 0);
1658  channel_reset_1 : in std_logic;
1659  soft_reset_1 : in std_logic;
1660  busy_1 : in std_logic;
1661  interface_reset_1 : out std_logic;
1662 
1663 
1664  full_mode_ctrl_0 : in STD_LOGIC_VECTOR (31 downto 0);
1665  full_mode_ctrl_1 : in STD_LOGIC_VECTOR (31 downto 0);
1666  full_mode_stat_0 : out STD_LOGIC_VECTOR (31 downto 0);
1667  full_mode_stat_1 : out STD_LOGIC_VECTOR (31 downto 0);
1668  FM_L1id_stat_0 : out std_logic_vector(31 downto 0);
1669  FM_L1id_stat_1 : out std_logic_vector(31 downto 0)
1670 
1671 
1672  );
1673 
1674 end component;
1675 
1676 component Full_Mode_CTTC
1677  generic(
1678  DEBUG : integer := 1;
1679 -- SIM : integer := 0;
1680  GTX_TRANSCEIVERS : boolean := false; -- true for GTX, false for GTH
1681  NUM_LINKS : integer := 2;
1682  RECOVER_CLK_FROM_RX_GBT : boolean := false;
1683  EXAMPLE_CONFIG_INDEPENDENT_LANES : integer := 1;
1684  EXAMPLE_LANE_WITH_START_CHAR : integer := 0; -- specifies lane with unique start frame ch
1685  EXAMPLE_WORDS_IN_BRAM : integer := 512; -- specifies amount of data in BRAM
1686  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
1687  STABLE_CLOCK_PERIOD : integer := 24;
1688  EXAMPLE_USE_CHIPSCOPE : integer := 1 -- Set to 1 to use Chipscope to drive re
1689  );
1690 
1691 
1692 port (
1693 -- GTREFCLK0_N_IN : in std_logic;
1694 -- GTREFCLK0_P_IN : in std_logic;
1695  GTREFCLK0 : in std_logic;
1696  pp_clock : in std_logic;
1697  RESET_BUTTON : in std_logic;
1698 
1699  app_clk_in : in std_logic;
1700 -- gtrxn_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1701 -- gtrxp_in : in std_logic_vector(NUM_LINKS-1 downto 0);
1702  gttxn_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1703  gttxp_out : out std_logic_vector(NUM_LINKS-1 downto 0);
1704 
1705  s_axis_tvalid_0 : in std_logic;
1706  s_axis_tlast_0 : in std_logic;
1707  s_axis_tready_0 : out std_logic;
1708  flx_bp_240_0 : in std_logic; --felix back pressure
1709  s_axis_tdata_0 : in std_logic_vector(31 downto 0);
1710  TXOUTCLK_0 : out std_logic;
1711  channel_reset_0 : in std_logic;
1712  soft_reset_0 : in std_logic;
1713  busy_0 : in std_logic;
1714  --replaced by fm_control
1715  --TestMode_0 : in std_logic;
1716  interface_reset_0 : out std_logic;
1717 
1718  s_axis_tvalid_1 : in std_logic;
1719  s_axis_tlast_1 : in std_logic;
1720  s_axis_tready_1 : out std_logic;
1721  flx_bp_240_1 : in std_logic; --felix back pressure
1722  s_axis_tdata_1 : in std_logic_vector(31 downto 0);
1723 -- TXOUTCLK_1 : out std_logic;
1724  channel_reset_1 : in std_logic;
1725  soft_reset_1 : in std_logic;
1726  busy_1 : in std_logic;
1727 -- TestMode_1 : in std_logic;
1728  interface_reset_1 : out std_logic;
1729  full_mode_ctrl_0 : in STD_LOGIC_VECTOR (31 downto 0);
1730  full_mode_ctrl_1 : in STD_LOGIC_VECTOR (31 downto 0);
1731  --full_mode_ctrl(0) = soft reset (must be toggled high then low)
1732  --full_mode_ctrl(1) = enable playout
1733  --full_mode_ctrl(2) = assert FM busy out
1734  --full_mode_ctrl(2) = assert LEMO
1735 
1736  full_mode_stat_0 : out STD_LOGIC_VECTOR (31 downto 0);
1737  full_mode_stat_1 : out STD_LOGIC_VECTOR (31 downto 0);
1738  --full_mode_stat(0) = 270 MHz MMCM locked
1739  --full_mode_stat(1) = reset done
1740  --full_mode_stat(1) = Start of Packet (SOP)
1741  --full_mode_stat(1) = End of Packet (EOP)
1742  --full_mode_stat(26 downto 16) = fifo fill level = fifo34_count
1743  FM_L1id_stat_0 : out std_logic_vector(31 downto 0);
1744  FM_L1id_stat_1 : out std_logic_vector(31 downto 0);
1745 
1746  --***** CTTC PORTS ***********************************
1747  gt_refclk_q219_c0 : in std_logic;
1748 -- Q9_CLK0_GTREFCLK_IN_P : in std_logic;
1749 -- Q9_CLK0_GTREFCLK_IN_N : in std_logic;
1750  DRP_CLK_IN : in std_logic;
1751  gt0_rxusrclk : out std_logic;
1752  TRACK_DATA_OUT : out std_logic;
1753  ttc_word_0 : out std_logic_vector(31 downto 0);
1754  ttc_word_1 : out std_logic_vector(31 downto 0);
1755  ttc_word_2 : out std_logic_vector(31 downto 0);
1756  ttc_word_3 : out std_logic_vector(31 downto 0);
1757  ttc_seq : out std_logic_vector(1 downto 0);
1758  ttc_status : out std_logic_vector(31 downto 0);
1759  ttc_reset : in std_logic;
1760  sys_top_reset : in std_logic;
1761  stop_ttc_info : in STD_LOGIC;
1762 
1763  cttc_cpllreset_in : in STD_LOGIC;
1764  gt0_cpllpd_in : in std_logic;
1765  gt0_rxbufreset_in : in STD_LOGIC;
1766  gt0_rxpcsreset_in : in STD_LOGIC;
1767  gt0_rxpmareset_in : in STD_LOGIC;
1768  gt0_rxcdrhold_in : in STD_LOGIC;
1769  gt0_rxpd_in : in STD_LOGIC;
1770 
1771  CTTC_RXN_IN : in std_logic;
1772  CTTC_RXP_IN : in std_logic;
1773 
1774  FM_CTTC_rxdata : out std_logic_vector (31 downto 0);
1775  FM_CTTC_rxcharisk : out std_logic_vector (3 downto 0);
1776  FM_CTTC_MGT_bus : out STD_LOGIC_VECTOR(31 DOWNTO 0);
1777  FM_CTTC_rxoutclk : out std_logic
1778 
1779  );
1780 
1781 end component;
1782 
1783 
1784 component packet_fifo
1785  Port (
1786  --Slave (input) side
1787  s_axis_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
1788  s_axis_tvalid : IN STD_LOGIC;
1789  s_axis_tlast : IN STD_LOGIC;
1790  s_axis_tready : OUT STD_LOGIC;
1791 
1792  --Master (output) side
1793  m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
1794  m_axis_tvalid : OUT STD_LOGIC;
1795  m_axis_tready : IN STD_LOGIC;
1796  m_axis_tlast : OUT STD_LOGIC;
1797 
1798  --control
1799 -- DATA_COUNT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
1800  WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
1801  RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
1802  fifo_full : out STD_LOGIC;
1803  clk_160 : in std_logic;
1804  clk_240 : in std_logic;
1805  RESET : in std_logic;
1806  flx_backpressure : in std_logic;
1807  flx_bp_enable : in std_logic;
1808  flx_bp_240 : out std_logic
1809  );
1810 end component;
1811 
1812 COMPONENT vio_top
1813  PORT (
1814  clk : IN STD_LOGIC;
1815  probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1816  probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1817  probe_in2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1818  probe_in3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1819  probe_in4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1820  probe_in5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1821  probe_in6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1822  probe_in7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1823  probe_in8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1824  probe_in9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1825  probe_in10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1826  probe_in11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1827  probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1828  probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1829  probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1830  probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1831  probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1832  probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
1833  probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
1834  );
1835 END COMPONENT;
1836 
1837 COMPONENT ila_hub_rst
1838 PORT (
1839  clk : IN STD_LOGIC;
1840  probe0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1841  probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1842  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
1843 );
1844 END COMPONENT;
1845 
1846 COMPONENT vio_ttc
1847  PORT (
1848  clk : IN STD_LOGIC;
1849  probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
1850  probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
1851  );
1852 END COMPONENT;
1853 
1854  signal ipbr_backplane : ipb_rbus;
1855  signal ipbw_backplane : ipb_wbus;
1856  signal ipbr_Processor : ipb_rbus;
1857  signal ipbw_Processor : ipb_wbus;
1858  signal ipb_clk : std_logic;
1859  signal ipb_rst : std_logic;
1860 -- signal ipbr_backplane : ipb_rbus_array(0 downto 0);
1861 -- signal ipbw_backplane : ipb_wbus_array(0 downto 0);
1862 
1863  signal geo_location : STD_LOGIC_VECTOR (7 downto 0);
1864  signal flx_bp_bus : STD_LOGIC_VECTOR (11 downto 0);
1865 
1866  signal pp_clock : std_logic;
1867  signal rt_clk : std_logic;
1868  signal backplane_control : std_logic_vector(31 downto 0);
1869 
1870  signal cttc_cpllreset_in : std_logic;
1871  signal cttc_cpllpd_in : STD_LOGIC;
1872  signal cttc_rxbufreset_in : STD_LOGIC;
1873  signal cttc_rxpcsreset_in : STD_LOGIC;
1874  signal cttc_rxpmareset_in : STD_LOGIC;
1875  signal cttc_rxcdrhold_in : STD_LOGIC;
1876  signal cttc_rxpd_in : STD_LOGIC;
1877 
1878  signal PKT_CLK : STD_LOGIC;
1879  signal CLK_40 : STD_LOGIC;
1880  signal clk_160 : std_logic;
1881  signal CLK_40_pin : STD_LOGIC;
1882  signal CLK_125 : STD_LOGIC;
1883  signal gp_button_i : STD_LOGIC;
1884  signal GTCLK_q218 : STD_LOGIC;
1885 -- AXI4 Streaming bus signals from Aurora Interface to Packet Processor
1886 
1887  signal bulk_m_tvalid_0 : STD_LOGIC;
1888  signal bulk_m_tlast_0 : STD_LOGIC;
1889  signal bulk_m_tdata_0 : STD_LOGIC_VECTOR (63 downto 0);
1890  signal bulk_m_header_marker_0 : STD_LOGIC;
1891  signal bulk_m_tail_marker_0 : STD_LOGIC;
1892  signal bulk_m_tready_0 : STD_LOGIC;
1893 
1894  signal bulk_fm_tvalid_0 : STD_LOGIC;
1895  signal bulk_fm_tlast_0 : STD_LOGIC;
1896  signal bulk_fm_tdata_0 : STD_LOGIC_VECTOR (31 downto 0);
1897  signal bulk_fm_tready_0 : STD_LOGIC;
1898  signal flx_bp_240_bulk_0 : STD_LOGIC;
1899 
1900  signal bulk_m_tvalid_1 : STD_LOGIC;
1901  signal bulk_m_tlast_1 : STD_LOGIC;
1902  signal bulk_m_tdata_1 : STD_LOGIC_VECTOR (63 downto 0);
1903  signal bulk_m_header_marker_1 : STD_LOGIC;
1904  signal bulk_m_tail_marker_1 : STD_LOGIC;
1905  signal bulk_m_tready_1 : STD_LOGIC;
1906 
1907  signal bulk_fm_tvalid_1 : STD_LOGIC;
1908  signal bulk_fm_tlast_1 : STD_LOGIC;
1909  signal bulk_fm_tdata_1 : STD_LOGIC_VECTOR (31 downto 0);
1910  signal bulk_fm_tready_1 : STD_LOGIC;
1911  signal flx_bp_240_bulk_1 : STD_LOGIC;
1912 
1913 
1914  signal bulk_m_tvalid_2 : STD_LOGIC;
1915  signal bulk_m_tlast_2 : STD_LOGIC;
1916  signal bulk_m_tdata_2 : STD_LOGIC_VECTOR (63 downto 0);
1917  signal bulk_m_header_marker_2 : STD_LOGIC;
1918  signal bulk_m_tail_marker_2 : STD_LOGIC;
1919  signal bulk_m_tready_2 : STD_LOGIC;
1920 
1921  signal bulk_fm_tvalid_2 : STD_LOGIC;
1922  signal bulk_fm_tlast_2 : STD_LOGIC;
1923  signal bulk_fm_tdata_2 : STD_LOGIC_VECTOR (31 downto 0);
1924  signal bulk_fm_tready_2 : STD_LOGIC;
1925  signal flx_bp_240_bulk_2 : STD_LOGIC;
1926 
1927  signal FM1_reset_0 : STD_LOGIC;
1928  signal FM1_reset_1 : STD_LOGIC;
1929  signal FM2_reset_0 : STD_LOGIC;
1930  signal FM2_reset_1 : STD_LOGIC;
1931 
1932  signal fm_soft_reset : STD_LOGIC;
1933 
1934  signal stage_fifo_level_tob_0 : STD_LOGIC_VECTOR (31 downto 0);
1935  signal stage_fifo_level_bulk_0 : STD_LOGIC_VECTOR (31 downto 0);
1936  signal stage_fifo_level_bulk_1 : STD_LOGIC_VECTOR (31 downto 0);
1937  signal stage_fifo_level_bulk_2 : STD_LOGIC_VECTOR (31 downto 0);
1938 
1939  signal stage_fifo_full_tob_0 : std_logic;
1940  signal stage_fifo_full_bulk_0 : std_logic;
1941  signal stage_fifo_full_bulk_1 : std_logic;
1942  signal stage_fifo_full_bulk_2 : std_logic;
1943 
1944  signal stage_fifo_busy_tob_0 : std_logic;
1945  signal stage_fifo_busy_bulk_0 : std_logic;
1946  signal stage_fifo_busy_bulk_1 : std_logic;
1947  signal stage_fifo_busy_bulk_2 : std_logic;
1948 
1949  signal stage_fifo_xoff_tob_0 : std_logic;
1950  signal stage_fifo_xoff_bulk_0 : std_logic;
1951  signal stage_fifo_xoff_bulk_1 : std_logic;
1952  signal stage_fifo_xoff_bulk_2 : std_logic;
1953 
1954  signal flx_backpressure_tob_0 : STD_LOGIC;
1955  signal flx_backpressure_bulk_0 : STD_LOGIC;
1956  signal flx_backpressure_bulk_1 : STD_LOGIC;
1957  signal flx_backpressure_bulk_2 : STD_LOGIC;
1958 
1959 
1960 
1961 -- channel Status signals from Aurora interface to Packet Processor
1962 
1963 
1964  signal CHANNEL_CTRL_0 : STD_LOGIC_VECTOR (31 downto 0);
1965  signal CHANNEL_STAT_0 : STD_LOGIC_VECTOR (31 downto 0);
1966  signal m_axi_rx_tdata_0 : std_logic_vector (63 downto 0);
1967  signal m_axi_rx_tvalid_0 : STD_LOGIC;
1968  signal m_axi_rx_tlast_0 : STD_LOGIC;
1969  signal m_axi_rx_tkeep_0 : std_logic_vector (7 downto 0);
1970 
1971  signal m_axi_ufc_rx_tdata_0 : STD_LOGIC_vector (63 downto 0);
1972  signal m_axi_ufc_rx_tvalid_0 : STD_LOGIC;
1973  signal m_axi_ufc_rx_tlast_0 : STD_LOGIC;
1974  signal user_clk_out_0 : STD_LOGIC;
1975 -- signal free_clk_out_0 : STD_LOGIC;
1976 
1977 -- signal RX_CHAN_UP_1 : STD_LOGIC;
1978 -- signal RX_HARD_ERR_1 : STD_LOGIC;
1979  signal CHANNEL_CTRL_1 : STD_LOGIC_VECTOR (31 downto 0);
1980  signal CHANNEL_STAT_1 : STD_LOGIC_VECTOR (31 downto 0);
1981  signal m_axi_rx_tdata_1 : std_logic_vector (63 downto 0);
1982  signal m_axi_rx_tvalid_1 : STD_LOGIC;
1983  signal m_axi_rx_tlast_1 : STD_LOGIC;
1984  signal m_axi_rx_tkeep_1 : std_logic_vector (7 downto 0);
1985  signal m_axi_ufc_rx_tdata_1 : STD_LOGIC_vector (63 downto 0);
1986  signal m_axi_ufc_rx_tvalid_1 : STD_LOGIC;
1987  signal m_axi_ufc_rx_tlast_1 : STD_LOGIC;
1988  signal user_clk_out_1 : STD_LOGIC;
1989 
1990 -- signal RX_CHAN_UP_2 : STD_LOGIC;
1991 -- signal RX_HARD_ERR_2 : STD_LOGIC;
1992  signal CHANNEL_CTRL_2 : STD_LOGIC_VECTOR (31 downto 0);
1993  signal CHANNEL_STAT_2 : STD_LOGIC_VECTOR (31 downto 0);
1994  signal m_axi_rx_tdata_2 : std_logic_vector (63 downto 0);
1995  signal m_axi_rx_tvalid_2 : STD_LOGIC;
1996  signal m_axi_rx_tlast_2 : STD_LOGIC;
1997  signal m_axi_rx_tkeep_2 : std_logic_vector (7 downto 0);
1998  signal m_axi_ufc_rx_tdata_2 : STD_LOGIC_vector (63 downto 0);
1999  signal m_axi_ufc_rx_tvalid_2 : STD_LOGIC;
2000  signal m_axi_ufc_rx_tlast_2 : STD_LOGIC;
2001  signal user_clk_out_2 : STD_LOGIC;
2002 
2003  signal CHANNEL_CTRL_3 : STD_LOGIC_VECTOR (31 downto 0);
2004  signal CHANNEL_STAT_3 : STD_LOGIC_VECTOR (31 downto 0);
2005  signal m_axi_rx_tdata_3 : std_logic_vector (63 downto 0);
2006  signal m_axi_rx_tvalid_3 : STD_LOGIC;
2007  signal m_axi_rx_tlast_3 : STD_LOGIC;
2008 -- signal m_axi_rx_tkeep_3 : std_logic_vector (7 downto 0);
2009  signal m_axi_ufc_rx_tdata_3 : STD_LOGIC_vector (63 downto 0);
2010  signal m_axi_ufc_rx_tvalid_3 : STD_LOGIC;
2011  signal m_axi_ufc_rx_tlast_3 : STD_LOGIC;
2012  signal user_clk_out_3 : STD_LOGIC;
2013 
2014  signal CHANNEL_CTRL_4 : STD_LOGIC_VECTOR (31 downto 0);
2015  signal CHANNEL_STAT_4 : STD_LOGIC_VECTOR (31 downto 0);
2016  signal m_axi_rx_tdata_4 : std_logic_vector (63 downto 0);
2017  signal m_axi_rx_tvalid_4 : STD_LOGIC;
2018  signal m_axi_rx_tlast_4 : STD_LOGIC;
2019  signal m_axi_ufc_rx_tdata_4 : STD_LOGIC_vector (63 downto 0);
2020  signal m_axi_ufc_rx_tvalid_4 : STD_LOGIC;
2021  signal m_axi_ufc_rx_tlast_4 : STD_LOGIC;
2022  signal user_clk_out_4 : STD_LOGIC;
2023 
2024  signal CHANNEL_CTRL_5 : STD_LOGIC_VECTOR (31 downto 0);
2025  signal CHANNEL_STAT_5 : STD_LOGIC_VECTOR (31 downto 0);
2026  signal m_axi_rx_tdata_5 : std_logic_vector (63 downto 0);
2027  signal m_axi_rx_tvalid_5 : STD_LOGIC;
2028  signal m_axi_rx_tlast_5 : STD_LOGIC;
2029 -- signal m_axi_rx_tkeep_5 : std_logic_vector (7 downto 0);
2030  signal m_axi_ufc_rx_tdata_5 : STD_LOGIC_vector (63 downto 0);
2031  signal m_axi_ufc_rx_tvalid_5 : STD_LOGIC;
2032  signal m_axi_ufc_rx_tlast_5 : STD_LOGIC;
2033  signal user_clk_out_5 : STD_LOGIC;
2034 
2035  signal CHANNEL_CTRL_6 : STD_LOGIC_VECTOR (31 downto 0);
2036  signal CHANNEL_STAT_6 : STD_LOGIC_VECTOR (31 downto 0);
2037  signal m_axi_rx_tdata_6 : std_logic_vector (63 downto 0);
2038  signal m_axi_rx_tvalid_6 : STD_LOGIC;
2039  signal m_axi_rx_tlast_6 : STD_LOGIC;
2040  signal m_axi_ufc_rx_tdata_6 : STD_LOGIC_vector (63 downto 0);
2041  signal m_axi_ufc_rx_tvalid_6 : STD_LOGIC;
2042  signal m_axi_ufc_rx_tlast_6 : STD_LOGIC;
2043  signal user_clk_out_6 : STD_LOGIC;
2044 
2045  signal CHANNEL_CTRL_7 : STD_LOGIC_VECTOR (31 downto 0);
2046  signal CHANNEL_STAT_7 : STD_LOGIC_VECTOR (31 downto 0);
2047  signal m_axi_rx_tdata_7 : std_logic_vector (63 downto 0);
2048  signal m_axi_rx_tvalid_7 : STD_LOGIC;
2049  signal m_axi_rx_tlast_7 : STD_LOGIC;
2050  signal m_axi_ufc_rx_tdata_7 : STD_LOGIC_vector (63 downto 0);
2051  signal m_axi_ufc_rx_tvalid_7 : STD_LOGIC;
2052  signal m_axi_ufc_rx_tlast_7 : STD_LOGIC;
2053  signal user_clk_out_7 : STD_LOGIC;
2054 
2055  signal CHANNEL_CTRL_8 : STD_LOGIC_VECTOR (31 downto 0);
2056  signal CHANNEL_STAT_8 : STD_LOGIC_VECTOR (31 downto 0);
2057  signal m_axi_rx_tdata_8 : std_logic_vector (63 downto 0);
2058  signal m_axi_rx_tvalid_8 : STD_LOGIC;
2059  signal m_axi_rx_tlast_8 : STD_LOGIC;
2060  signal m_axi_ufc_rx_tdata_8 : STD_LOGIC_vector (63 downto 0);
2061  signal m_axi_ufc_rx_tvalid_8 : STD_LOGIC;
2062  signal m_axi_ufc_rx_tlast_8 : STD_LOGIC;
2063  signal user_clk_out_8 : STD_LOGIC;
2064 
2065  signal CHANNEL_CTRL_9 : STD_LOGIC_VECTOR (31 downto 0);
2066  signal CHANNEL_STAT_9 : STD_LOGIC_VECTOR (31 downto 0);
2067  signal m_axi_rx_tdata_9 : std_logic_vector (63 downto 0);
2068  signal m_axi_rx_tvalid_9 : STD_LOGIC;
2069  signal m_axi_rx_tlast_9 : STD_LOGIC;
2070  signal m_axi_ufc_rx_tdata_9 : STD_LOGIC_vector (63 downto 0);
2071  signal m_axi_ufc_rx_tvalid_9 : STD_LOGIC;
2072  signal m_axi_ufc_rx_tlast_9 : STD_LOGIC;
2073  signal user_clk_out_9 : STD_LOGIC;
2074 
2075  signal CHANNEL_CTRL_10 : STD_LOGIC_VECTOR (31 downto 0);
2076  signal CHANNEL_STAT_10 : STD_LOGIC_VECTOR (31 downto 0);
2077  signal m_axi_rx_tdata_10 : std_logic_vector (63 downto 0);
2078  signal m_axi_rx_tvalid_10 : STD_LOGIC;
2079  signal m_axi_rx_tlast_10 : STD_LOGIC;
2080  signal m_axi_ufc_rx_tdata_10 : STD_LOGIC_vector (63 downto 0);
2081  signal m_axi_ufc_rx_tvalid_10 : STD_LOGIC;
2082  signal m_axi_ufc_rx_tlast_10 : STD_LOGIC;
2083  signal user_clk_out_10 : STD_LOGIC;
2084 
2085  signal CHANNEL_CTRL_11 : STD_LOGIC_VECTOR (31 downto 0);
2086  signal CHANNEL_STAT_11 : STD_LOGIC_VECTOR (31 downto 0);
2087  signal m_axi_rx_tdata_11 : std_logic_vector (63 downto 0);
2088  signal m_axi_rx_tvalid_11 : STD_LOGIC;
2089  signal m_axi_rx_tlast_11 : STD_LOGIC;
2090  signal m_axi_ufc_rx_tdata_11 : STD_LOGIC_vector (63 downto 0);
2091  signal m_axi_ufc_rx_tvalid_11 : STD_LOGIC;
2092  signal m_axi_ufc_rx_tlast_11 : STD_LOGIC;
2093  signal user_clk_out_11 : STD_LOGIC;
2094 
2095  signal CHANNEL_CTRL_12 : STD_LOGIC_VECTOR (31 downto 0);
2096  signal CHANNEL_STAT_12 : STD_LOGIC_VECTOR (31 downto 0);
2097  signal m_axi_rx_tdata_12 : std_logic_vector (63 downto 0);
2098  signal m_axi_rx_tvalid_12 : STD_LOGIC;
2099  signal m_axi_rx_tlast_12 : STD_LOGIC;
2100  signal m_axi_ufc_rx_tdata_12 : STD_LOGIC_vector (63 downto 0);
2101  signal m_axi_ufc_rx_tvalid_12 : STD_LOGIC;
2102  signal m_axi_ufc_rx_tlast_12 : STD_LOGIC;
2103  signal user_clk_out_12 : STD_LOGIC;
2104  signal free_clk_out_12 : STD_LOGIC;
2105 
2106  signal CHANNEL_CTRL_13 : STD_LOGIC_VECTOR (31 downto 0);
2107  signal CHANNEL_STAT_13 : STD_LOGIC_VECTOR (31 downto 0);
2108  signal m_axi_rx_tdata_13 : std_logic_vector (63 downto 0);
2109  signal m_axi_rx_tvalid_13 : STD_LOGIC;
2110  signal m_axi_rx_tlast_13 : STD_LOGIC;
2111  signal m_axi_ufc_rx_tdata_13 : STD_LOGIC_vector (63 downto 0);
2112  signal m_axi_ufc_rx_tvalid_13 : STD_LOGIC;
2113  signal m_axi_ufc_rx_tlast_13 : STD_LOGIC;
2114  signal user_clk_out_13 : STD_LOGIC;
2115  signal free_clk_out_13 : STD_LOGIC;
2116 
2117  signal CHANNEL_CTRL_14 : STD_LOGIC_VECTOR (31 downto 0);
2118  signal CHANNEL_STAT_14 : STD_LOGIC_VECTOR (31 downto 0);
2119  signal m_axi_rx_tdata_14 : std_logic_vector (63 downto 0);
2120  signal m_axi_rx_tvalid_14 : STD_LOGIC;
2121  signal m_axi_rx_tlast_14 : STD_LOGIC;
2122  signal m_axi_ufc_rx_tdata_14 : STD_LOGIC_vector (63 downto 0);
2123  signal m_axi_ufc_rx_tvalid_14 : STD_LOGIC;
2124  signal m_axi_ufc_rx_tlast_14 : STD_LOGIC;
2125  signal user_clk_out_14 : STD_LOGIC;
2126  signal free_clk_out_14 : STD_LOGIC;
2127 
2128  signal CHANNEL_CTRL_15 : STD_LOGIC_VECTOR (31 downto 0);
2129  signal CHANNEL_STAT_15 : STD_LOGIC_VECTOR (31 downto 0);
2130  signal m_axi_rx_tdata_15 : std_logic_vector (63 downto 0);
2131  signal m_axi_rx_tvalid_15 : STD_LOGIC;
2132  signal m_axi_rx_tlast_15 : STD_LOGIC;
2133  signal m_axi_ufc_rx_tdata_15 : STD_LOGIC_vector (63 downto 0);
2134  signal m_axi_ufc_rx_tvalid_15 : STD_LOGIC;
2135  signal m_axi_ufc_rx_tlast_15 : STD_LOGIC;
2136  signal user_clk_out_15 : STD_LOGIC;
2137  signal free_clk_out_15 : STD_LOGIC;
2138 
2139  signal CHANNEL_CTRL_16 : STD_LOGIC_VECTOR (31 downto 0);
2140  signal CHANNEL_STAT_16 : STD_LOGIC_VECTOR (31 downto 0);
2141  signal m_axi_rx_tdata_16 : std_logic_vector (63 downto 0);
2142  signal m_axi_rx_tvalid_16 : STD_LOGIC;
2143  signal m_axi_rx_tlast_16 : STD_LOGIC;
2144  signal m_axi_ufc_rx_tdata_16 : STD_LOGIC_vector (63 downto 0);
2145  signal m_axi_ufc_rx_tvalid_16 : STD_LOGIC;
2146  signal m_axi_ufc_rx_tlast_16 : STD_LOGIC;
2147  signal user_clk_out_16 : STD_LOGIC;
2148 
2149  signal CHANNEL_CTRL_17 : STD_LOGIC_VECTOR (31 downto 0);
2150  signal CHANNEL_STAT_17 : STD_LOGIC_VECTOR (31 downto 0);
2151  signal m_axi_rx_tdata_17 : std_logic_vector (63 downto 0);
2152  signal m_axi_rx_tvalid_17 : STD_LOGIC;
2153  signal m_axi_rx_tlast_17 : STD_LOGIC;
2154  signal m_axi_ufc_rx_tdata_17 : STD_LOGIC_vector (63 downto 0);
2155  signal m_axi_ufc_rx_tvalid_17 : STD_LOGIC;
2156  signal m_axi_ufc_rx_tlast_17 : STD_LOGIC;
2157  signal user_clk_out_17 : STD_LOGIC;
2158 
2159  signal CHANNEL_CTRL_18 : STD_LOGIC_VECTOR (31 downto 0);
2160  signal CHANNEL_STAT_18 : STD_LOGIC_VECTOR (31 downto 0);
2161  signal m_axi_rx_tdata_18 : std_logic_vector (63 downto 0);
2162  signal m_axi_rx_tvalid_18 : STD_LOGIC;
2163  signal m_axi_rx_tlast_18 : STD_LOGIC;
2164  signal m_axi_ufc_rx_tdata_18 : STD_LOGIC_vector (63 downto 0);
2165  signal m_axi_ufc_rx_tvalid_18 : STD_LOGIC;
2166  signal m_axi_ufc_rx_tlast_18 : STD_LOGIC;
2167  signal user_clk_out_18 : STD_LOGIC;
2168 
2169  signal CHANNEL_CTRL_19 : STD_LOGIC_VECTOR (31 downto 0);
2170  signal CHANNEL_STAT_19 : STD_LOGIC_VECTOR (31 downto 0);
2171  signal m_axi_rx_tdata_19 : std_logic_vector (63 downto 0);
2172  signal m_axi_rx_tvalid_19 : STD_LOGIC;
2173  signal m_axi_rx_tlast_19 : STD_LOGIC;
2174  signal m_axi_ufc_rx_tdata_19 : STD_LOGIC_vector (63 downto 0);
2175  signal m_axi_ufc_rx_tvalid_19 : STD_LOGIC;
2176  signal m_axi_ufc_rx_tlast_19 : STD_LOGIC;
2177  signal user_clk_out_19 : STD_LOGIC;
2178 
2179  signal CHANNEL_CTRL_20 : STD_LOGIC_VECTOR (31 downto 0);
2180  signal CHANNEL_STAT_20 : STD_LOGIC_VECTOR (31 downto 0);
2181  signal m_axi_rx_tdata_20 : std_logic_vector (63 downto 0);
2182  signal m_axi_rx_tvalid_20 : STD_LOGIC;
2183  signal m_axi_rx_tlast_20 : STD_LOGIC;
2184  signal m_axi_ufc_rx_tdata_20 : STD_LOGIC_vector (63 downto 0);
2185  signal m_axi_ufc_rx_tvalid_20 : STD_LOGIC;
2186  signal m_axi_ufc_rx_tlast_20 : STD_LOGIC;
2187  signal user_clk_out_20 : STD_LOGIC;
2188 
2189  signal CHANNEL_CTRL_21 : STD_LOGIC_VECTOR (31 downto 0);
2190  signal CHANNEL_STAT_21 : STD_LOGIC_VECTOR (31 downto 0);
2191  signal m_axi_rx_tdata_21 : std_logic_vector (63 downto 0);
2192  signal m_axi_rx_tvalid_21 : STD_LOGIC;
2193  signal m_axi_rx_tlast_21 : STD_LOGIC;
2194  signal m_axi_ufc_rx_tdata_21 : STD_LOGIC_vector (63 downto 0);
2195  signal m_axi_ufc_rx_tvalid_21 : STD_LOGIC;
2196  signal m_axi_ufc_rx_tlast_21 : STD_LOGIC;
2197  signal user_clk_out_21 : STD_LOGIC;
2198 
2199  signal CHANNEL_CTRL_22 : STD_LOGIC_VECTOR (31 downto 0);
2200  signal CHANNEL_STAT_22 : STD_LOGIC_VECTOR (31 downto 0);
2201  signal m_axi_rx_tdata_22 : std_logic_vector (63 downto 0);
2202  signal m_axi_rx_tvalid_22 : STD_LOGIC;
2203  signal m_axi_rx_tlast_22 : STD_LOGIC;
2204  signal m_axi_ufc_rx_tdata_22 : STD_LOGIC_vector (63 downto 0);
2205  signal m_axi_ufc_rx_tvalid_22 : STD_LOGIC;
2206  signal m_axi_ufc_rx_tlast_22 : STD_LOGIC;
2207  signal user_clk_out_22 : STD_LOGIC;
2208 
2209  signal CHANNEL_CTRL_23 : STD_LOGIC_VECTOR (31 downto 0);
2210  signal CHANNEL_STAT_23 : STD_LOGIC_VECTOR (31 downto 0);
2211  signal m_axi_rx_tdata_23 : std_logic_vector (63 downto 0);
2212  signal m_axi_rx_tvalid_23 : STD_LOGIC;
2213  signal m_axi_rx_tlast_23 : STD_LOGIC;
2214  signal m_axi_ufc_rx_tdata_23 : STD_LOGIC_vector (63 downto 0);
2215  signal m_axi_ufc_rx_tvalid_23 : STD_LOGIC;
2216  signal m_axi_ufc_rx_tlast_23 : STD_LOGIC;
2217  signal user_clk_out_23 : STD_LOGIC;
2218 
2219 
2220  signal channel_enable_vio : std_logic_vector (23 downto 0);
2221  signal first_chan_vio : std_logic_vector (4 downto 0);
2222  signal last_chan_vio : std_logic_vector (4 downto 0);
2223  signal TTC_ignore_vio : std_logic;
2224  signal debug_ctrl_vio : std_logic;
2225 
2226  signal pp0_m_axi_tdata : std_logic_vector (63 downto 0);
2227  signal pp0_m_axi_tvalid : STD_LOGIC;
2228  signal pp0_m_axi_tlast : STD_LOGIC;
2229  signal pp0_m_axi_tready : STD_LOGIC;
2230 
2231  signal pp_soft_reset_vio : STD_LOGIC;
2232  signal pp_reset : STD_LOGIC;
2233 
2234 
2235 
2236  signal fifo_AXI4_TDATA : std_logic_vector (31 downto 0);
2237  signal fifo_AXI4_TVALID : STD_LOGIC;
2238  signal felix_AXI4_TREADY : STD_LOGIC;
2239  signal fifo_AXI4_tlast : STD_LOGIC;
2240 
2241 
2242  signal ppout_fifo_AXI4_TDATA : std_logic_vector (31 downto 0);
2243  signal ppout_fifo_AXI4_TVALID : STD_LOGIC;
2244  signal felix_ch1_AXI4_TREADY : STD_LOGIC;
2245  signal ppout_fifo_AXI4_tlast : STD_LOGIC;
2246  signal flx_bp_240_tob_0 : STD_LOGIC;
2247 
2248 
2249 
2250  signal FM_TXOUTCLK : STD_LOGIC;
2251  signal FM_TXOUTCLK_2 : STD_LOGIC;
2252 -- signal FM_reset_0 : STD_LOGIC;
2253 -- signal FM_reset_1 : STD_LOGIC;
2254  signal GTREFCLK_Q217_C0 : STD_LOGIC;
2255 
2256  signal gp_button_ibuf : STD_LOGIC;
2257  signal vio_reset : STD_LOGIC;
2258  signal sys_top_reset : STD_LOGIC;
2259  signal MASTER_RESET : STD_LOGIC;
2260  signal rx_GTReset : STD_LOGIC;
2261  signal rx_reset : STD_LOGIC;
2262 
2263 --TTC signals
2264 
2265  signal ttc_word_0 : std_logic_vector(31 downto 0);
2266  signal ttc_word_1 : std_logic_vector(31 downto 0);
2267  signal ttc_word_2 : std_logic_vector(31 downto 0);
2268  signal ttc_word_3 : std_logic_vector(31 downto 0);
2269  signal ttc_seq : std_logic_vector(1 downto 0);
2270  signal cttc_usrclk : std_logic;
2271  signal L1A : std_logic;
2272  signal l1id_mis_stretch : std_logic;
2273  signal vio_chan_reset : std_logic;
2274  signal sys_top_reset_b : std_logic;
2275 
2276  signal spi_pwr2 : std_logic;
2277  signal spi_pwr1 : std_logic := '0';
2278 
2279  signal ro_user_clock : STD_LOGIC;
2280  signal ro_controller_reset : STD_LOGIC;
2281  signal ro_txcharisk : std_logic_vector(3 downto 0);
2282  signal ro_txdata : std_logic_vector(31 downto 0);
2283  signal ro_status : std_logic_vector(7 downto 0);
2284  signal ttc_status : std_logic_vector(31 downto 0);
2285  signal ttc_reset : std_logic;
2286  signal hub_link_reset : std_logic;
2287  signal multichannel_busy : std_logic;
2288  signal combined_busy : std_logic;
2289  signal lemo_i : std_logic;
2290 
2291  signal full_mode_stat_tob_0 : std_logic_vector(31 downto 0);
2292  signal full_mode_stat_bulk_0 : std_logic_vector(31 downto 0);
2293  signal full_mode_stat_bulk_1 : std_logic_vector(31 downto 0);
2294  signal full_mode_stat_bulk_2 : std_logic_vector(31 downto 0);
2295 
2296  signal FM_L1id_stat_tob_0 : std_logic_vector(31 downto 0);
2297  signal FM_L1id_stat_bulk_0 : std_logic_vector(31 downto 0);
2298  signal FM_L1id_stat_bulk_1 : std_logic_vector(31 downto 0);
2299  signal FM_L1id_stat_bulk_2 : std_logic_vector(31 downto 0);
2300 
2301  signal full_mode_ctrl_tob_0 : std_logic_vector(31 downto 0);
2302  signal full_mode_ctrl_bulk_0 : std_logic_vector(31 downto 0);
2303  signal full_mode_ctrl_bulk_1 : std_logic_vector(31 downto 0);
2304  signal full_mode_ctrl_bulk_2 : std_logic_vector(31 downto 0);
2305 
2306  signal hub_link_reset_b : std_logic;
2307  signal hub_reset : std_logic;
2308  signal hub_rst_tmr : std_logic;
2309 
2310  signal gt_refclk_q219_c0 : std_logic;
2311 
2312  signal FM_CTTC_rxdata : std_logic_vector (31 downto 0);
2313  signal FM_CTTC_rxcharisk : std_logic_vector (3 downto 0);
2314  signal FM_CTTC_MGT_bus : STD_LOGIC_VECTOR(31 DOWNTO 0);
2315  signal FM_CTTC_rxoutclk : std_logic;
2316  signal BP_CTTC_rxdata : std_logic_vector (31 downto 0);
2317  signal BP_CTTC_rxcharisk : std_logic_vector (3 downto 0);
2318  signal BP_CTTC_MGT_bus : STD_LOGIC_VECTOR(31 DOWNTO 0);
2319  signal BP_CTTC_rxoutclk : std_logic;
2320  signal ttc_mux_ctrl : std_logic;
2321 
2322 begin
2323 
2324  reset_top : system_top_reset
2325  generic map (
2326  max_count => x"0000FFFF"
2327  )
2328  port map (
2329  clk40 => CLK_40,
2330  rod_button => gp_button_i,
2331  sys_top_reset => sys_top_reset,
2332  sys_top_reset_b => sys_top_reset_b
2333 
2334  );
2335 
2336 
2337 
2338 --phy_resetn <= sys_top_reset_b;
2339 t_pod0_rst_b <= sys_top_reset_b;
2340 t_pod1_rst_b <= sys_top_reset_b;
2341 t_pod2_rst_b <= sys_top_reset_b;
2342 r_pod_rst_b <= sys_top_reset_b;
2343 
2344 phy_reset : system_top_reset
2345  generic map (
2346  max_count => x"02625A00" --1 second
2347  )
2348  port map (
2349  clk40 => CLK_40,
2350  rod_button => gp_button_i,
2351  sys_top_reset => open,
2352  sys_top_reset_b => phy_resetn
2353  );
2354 
2355 
2356 
2357 
2358 --hub_link_reset_b <= not hub_link_reset;
2359 --hub_reset <= sys_top_reset or hub_rst_tmr;
2360 --hub_reset <= sys_top_reset;
2361 
2362  proc_clock_gen : packet_processor_clock
2363  port map (
2364  -- Clock out ports
2365  pp_clock => pp_clock,
2366  rt_clock => rt_clk,
2367  -- Status and control signals
2368  locked => open,
2369  -- Clock in ports
2370  clk_in1 => CLK_40
2371  --clk_in1 => CLK_40_pin
2372  );
2373 
2374 
2375 top_vio : vio_top
2376  PORT MAP (
2377  clk => CLK_40,
2378  probe_in0(0) => MASTER_RESET,
2379  probe_in1(0) => sys_top_reset,
2380  probe_in2(0) => gp_button_i,
2381  probe_in3(0) => lemo_i,
2382  probe_in4(0) => rotary_switch(0),
2383  probe_in5(0) => rotary_switch(1),
2384  probe_in6(0) => rotary_switch(2),
2385  probe_in7(0) => rotary_switch(3),
2386  probe_in8(0) => CHANNEL_STAT_3(0),
2387  probe_in9(0) => CHANNEL_STAT_4(0),
2388  probe_in10(0) => CHANNEL_STAT_5(0),
2389  probe_in11(0) =>backplane_control(0),
2390  probe_out0(0) => vio_reset,
2391  probe_out1(0) => cttc_cpllpd_in,
2392  probe_out2(0) => cttc_rxbufreset_in,
2393  probe_out3(0) => cttc_rxpcsreset_in,
2394  probe_out4(0) => cttc_rxpmareset_in,
2395  probe_out5(0) => cttc_rxcdrhold_in,
2396  probe_out6(0) => cttc_rxpd_in
2397  );
2398 
2399 
2400 
2401  ipbus_blk : rod_system
2402  generic map (
2403  GLOBAL_DATE => GLOBAL_DATE,
2404  GLOBAL_TIME => GLOBAL_TIME,
2405  GLOBAL_VER => GLOBAL_VER,
2406  GLOBAL_SHA => GLOBAL_SHA,
2407  TOP_VER => TOP_VER,
2408  TOP_SHA => TOP_SHA,
2409  CON_VER => CON_VER,
2410  CON_SHA => CON_SHA,
2411  HOG_VER => HOG_VER,
2412  HOG_SHA => HOG_SHA,
2413 
2414  --IPBus XML
2415  XML_SHA => XML_SHA,
2416  XML_VER => XML_VER,
2417 
2418  ROD_JFEX_SHA => ROD_JFEX_SHA,
2419  ROD_JFEX_VER => ROD_JFEX_VER,
2420 
2421  jfex_rod => jfex_rod,
2422  efex_rod => efex_rod,
2423  golden_rod => golden_rod,
2424  --------------------------------------------------
2425  Module_ID => Module_ID,
2426 -- XmlVersion => XML_VER,
2427  BuildTimeAndDate => GLOBAL_DATE,
2428  FirmwareVersion => GLOBAL_SHA
2429  )
2430 
2431  port map (
2432  ipbr_backplane => ipbr_backplane,
2433  ipbw_backplane => ipbw_backplane,
2434  ipbr_Processor => ipbr_Processor,
2435  ipbw_Processor => ipbw_Processor,
2436  ipb_clk => ipb_clk,
2437  ipb_rst => ipb_rst,
2438  CLK_125 => CLK_125,
2439  gtx_clk_bufg_out => gtx_clk_bufg_out,
2440 
2441 
2442  phy_resetn => open,
2443 
2444  -- RGMII Interface
2445  ------------------
2446  rgmii_txd => rgmii_txd,
2447  rgmii_tx_ctl => rgmii_tx_ctl,
2448  rgmii_txc => rgmii_txc,
2449  rgmii_rxd => rgmii_rxd,
2450  rgmii_rx_ctl => rgmii_rx_ctl,
2451  rgmii_rxc => rgmii_rxc,
2452 
2453  -- MDIO Interface
2454  -----------------
2455  mdio => mdio,
2456  mdc => mdc,
2457  reset_error => reset_error,
2458 
2459  --LEDs
2460  -----------------
2461  leds => leds,
2462  userled => userled,
2463 
2464  --Rotary Switch
2465  --------------------
2466  rotary_switch => rotary_switch,
2467 
2468 
2469  -- GPIO Interface
2470  -------------------
2471  gp_button => '1',
2472  test1_2 => '0',
2473  test1_3 => '0',
2474  test1_4 => '0',
2475  test1_5 => '0',
2476  t_wrn_b => t_wrn_b,
2477  smbalert_b => smbalert_b,
2478  -- gpio2_tri_i(7) => ,
2479  -- gpio2_tri_i(8) => ,
2480  ck_pll_lock => ck_pll_lock,
2481  ck_int => ck_int,
2482  phy_int => phy_int,
2483  t_pod0_int => t_pod0_int,
2484  t_pod1_int => t_pod1_int,
2485  t_pod2_int => t_pod2_int,
2486  r_pod_int => r_pod_int,
2487  loc_addr1 => loc_addr1,
2488  loc_addr2 => loc_addr2,
2489  loc_addr3 => loc_addr3,
2490  loc_addr4 => loc_addr4,
2491  loc_addr5 => loc_addr5,
2492  loc_addr6 => loc_addr6,
2493  loc_addr7 => loc_addr7,
2494  loc_addr8 => loc_addr8,
2495 
2496 -- rod_gp_led => open,
2497  FP_GP_LED_B => open,
2498  FP_RUN_LED_B => open,
2499  lemo => open,
2500  -- gpio_tri_o(4) => ,
2501  pwr_con3 => open,
2502 -- pwr_con4 => pwr_con4,
2503  pwr_con4 => open,
2504  -- gpio_tri_o(7) => ,
2505  ck_pwr_dnb => open,
2506  ref_clk_sel => open,
2507  ck_syncb => open,
2508 -- phy_rst_n => open,
2509 -- t_pod0_rst_b => t_pod0_rst_b,
2510 -- t_pod1_rst_b => t_pod1_rst_b,
2511 -- t_pod2_rst_b => t_pod2_rst_b,
2512 -- r_pod_rst_b => r_pod_rst_b,
2513  t_pod0_rst_b => open,
2514  t_pod1_rst_b => open,
2515  t_pod2_rst_b => open,
2516  r_pod_rst_b => open,
2517 
2518  --Configuration Flash Interface
2519  ---------------------------------
2520  EMC_INTF_addr => EMC_INTF_addr,
2521  EMC_INTF_ce_n => EMC_INTF_ce_n,
2522  EMC_INTF_oen => EMC_INTF_oen,
2523  EMC_INTF_wen => EMC_INTF_wen,
2524  emc_intf_dq_io => emc_intf_dq_io,
2525 
2526  --I2C 1,0 interface
2527  ----------------------------------
2528  iic_1_scl_io => iic_1_scl_io,
2529  iic_1_sda_io => iic_1_sda_io,
2530  iic_scl_io => iic_scl_io,
2531  iic_sda_io => iic_sda_io,
2532 
2533  --SPI Interface
2534  ------------------------------------
2535  CK_SPI_MOSI => CK_SPI_MOSI,
2536  CK_SPI_MISO => CK_SPI_MISO,
2537  CK_SPI_CK => CK_SPI_CK,
2538 -- CK_SPI_LE => CK_SPI_LE,
2539  CK_SPI_LE => open,
2540 
2541  --XADC interface
2542  --------------------------------------
2543  Vp_Vn_v_n => Vp_Vn_v_n,
2544  Vp_Vn_v_p => Vp_Vn_v_p
2545 
2546 
2547 
2548 
2549  );
2550 
2551 
2552 
2553  geo_location(0) <= loc_addr1;
2554  geo_location(1) <= loc_addr2;
2555  geo_location(2) <= loc_addr3;
2556  geo_location(3) <= loc_addr4;
2557  geo_location(4) <= loc_addr5;
2558  geo_location(5) <= loc_addr6;
2559  geo_location(6) <= loc_addr7;
2560  geo_location(7) <= loc_addr8;
2561 -------------------------------------IMPORTANT---------------------------------------------------------------------------------------------
2562 --Ports on the backplane block refer to Logical Slot mapping
2563 --At this level there is a remapping from Logical slots to physical slots (left to Right in the Shelf)
2564 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2565  backplane : jfex_backplane
2566  port map (
2567  pp_clock => pp_clock,
2568  backplane_control => backplane_control,
2569 -- cttc_cpllreset_in => cttc_cpllreset_in,
2570  cttc_cpllpd_in => cttc_cpllpd_in,
2571  cttc_rxbufreset_in => cttc_rxbufreset_in,
2572  cttc_rxpcsreset_in => cttc_rxpcsreset_in,
2573  cttc_rxpmareset_in => cttc_rxpmareset_in,
2574  cttc_rxcdrhold_in => cttc_rxcdrhold_in,
2575  cttc_rxpd_in => cttc_rxpd_in,
2576 
2577  CLK_125 => CLK_125,
2578  CLK_160 => CLK_160,
2579  GT_RESET_IN => '0',
2580  RESET => '0',
2581  vio_chan_reset => vio_chan_reset,
2582  sys_top_reset => sys_top_reset,
2583 
2584 
2585  GTCLK_q112_c0p => GTCLK_q112_c0p,
2586  GTCLK_q112_c0n => GTCLK_q112_c0n,
2587  GTCLK_q115_c0p => GTCLK_q115_c0p,
2588  GTCLK_q115_c0n => GTCLK_q115_c0n,
2589 
2590  GTCLK_q118_c0p => GTCLK_q118_c0p,
2591  GTCLK_q118_c0n => GTCLK_q118_c0n,
2592 
2593  GTCLK_q211_c0p => GTCLK_q211_c0p,
2594  GTCLK_q211_c0n => GTCLK_q211_c0n,
2595 
2596  GTCLK_q214_c0p => GTCLK_q214_c0p,
2597  GTCLK_q214_c0n => GTCLK_q214_c0n,
2598 
2599  GTCLK_q217_c0p => GTCLK_q217_c0p,
2600  GTCLK_q217_c0n => GTCLK_q217_c0n,
2601 
2602 -- GTCLK_q219_c0p => GTCLK_q219_c0p,
2603 -- GTCLK_q219_c0n => GTCLK_q219_c0n,
2604  gt_refclk_q219_c0 => gt_refclk_q219_c0,
2605 
2606 
2607 --Ports on the backplane block refer to Logical Slot mapping
2608 --slot 4 lane 1 (keep logical map for RXP/RXN)
2609 RXP_0 => RXP_0,
2610 RXN_0 => RXN_0,
2611 
2612 --RX_CHAN_UP_0 => open,
2613 --RX_HARD_ERR_0 => open,
2614 
2615 CHANNEL_CTRL_0 => CHANNEL_CTRL_12,
2616 CHANNEL_STAT_0 => CHANNEL_STAT_12,
2617 m_axi_rx_tdata_0 => m_axi_rx_tdata_12,
2618 -- m_axi_rx_tkeep_3 => m_axi_rx_tkeep_3,
2619 --m_axi_rx_tkeep_0 => open,
2620 m_axi_rx_tvalid_0 => m_axi_rx_tvalid_12,
2621 m_axi_rx_tlast_0 => m_axi_rx_tlast_12,
2622  -- User Flow Control RX Inteface
2623 m_axi_ufc_rx_tdata_0 => m_axi_ufc_rx_tdata_12(31 downto 0),
2624 m_axi_ufc_rx_tkeep_0 => open,
2625 m_axi_ufc_rx_tvalid_0 => m_axi_ufc_rx_tvalid_12,
2626 m_axi_ufc_rx_tlast_0 => m_axi_ufc_rx_tlast_12,
2627 USER_CLK_OUT_0 => user_clk_out_12,
2628 
2629 --Ports on the backplane block refer to Logical Slot mapping
2630 --slot 4 lane 2 (keep logical map for RXP/RXN)
2631 RXP_1 => RXP_1,
2632 RXN_1 => RXN_1,
2633 
2634 --RX_CHAN_UP_1 => RX_CHAN_UP_1,
2635 --RX_HARD_ERR_1 => RX_HARD_ERR_1,
2636 CHANNEL_CTRL_1 => CHANNEL_CTRL_13,
2637 CHANNEL_STAT_1 => CHANNEL_STAT_13,
2638 m_axi_rx_tdata_1 => m_axi_rx_tdata_13,
2639 -- m_axi_rx_tkeep_3 => m_axi_rx_tkeep_3,
2640 --m_axi_rx_tkeep_1 => open,
2641 m_axi_rx_tvalid_1 => m_axi_rx_tvalid_13,
2642 m_axi_rx_tlast_1 => m_axi_rx_tlast_13,
2643  -- User Flow Control RX Inteface
2644 m_axi_ufc_rx_tdata_1 => m_axi_ufc_rx_tdata_13(31 downto 0),
2645 m_axi_ufc_rx_tkeep_1 => open,
2646 m_axi_ufc_rx_tvalid_1 => m_axi_ufc_rx_tvalid_13,
2647 m_axi_ufc_rx_tlast_1 => m_axi_ufc_rx_tlast_13,
2648 USER_CLK_OUT_1 => user_clk_out_13,
2649 
2650 --slot 4 lane 3 (keep logical map for RXP/RXN)
2651 --Ports on the backplane block refer to Logical Slot mapping
2652 RXP_2 => RXP_2,
2653 RXN_2 => RXN_2,
2654 
2655 --RX_CHAN_UP_2 => RX_CHAN_UP_2,
2656 --RX_HARD_ERR_2 => RX_HARD_ERR_2,
2657 CHANNEL_CTRL_2 => CHANNEL_CTRL_15,
2658 CHANNEL_STAT_2 => CHANNEL_STAT_15,
2659 m_axi_rx_tdata_2 => m_axi_rx_tdata_15,
2660 -- m_axi_rx_tkeep_3 => m_axi_rx_tkeep_3,
2661 --m_axi_rx_tkeep_2 => open,
2662 m_axi_rx_tvalid_2 => m_axi_rx_tvalid_15,
2663 m_axi_rx_tlast_2 => m_axi_rx_tlast_15,
2664  -- User Flow Control RX Inteface
2665 m_axi_ufc_rx_tdata_2 => m_axi_ufc_rx_tdata_15(31 downto 0),
2666 m_axi_ufc_rx_tkeep_2 => open,
2667 
2668 m_axi_ufc_rx_tvalid_2 => m_axi_ufc_rx_tvalid_15,
2669 m_axi_ufc_rx_tlast_2 => m_axi_ufc_rx_tlast_15,
2670 USER_CLK_OUT_2 => user_clk_out_15,
2671 
2672 --Ports on the backplane block refer to Logical Slot mapping
2673 -----aurora slot 4 lane 4----------------(keep logical map for RXP/RXN)
2674  RXP_3 => RXP_3,
2675  RXN_3 => RXN_3,
2676 
2677 -- RX_CHAN_UP_3 => RX_CHAN_UP_3,
2678 -- RX_HARD_ERR_3 => RX_HARD_ERR_3,
2679  CHANNEL_CTRL_3 => CHANNEL_CTRL_14,
2680  CHANNEL_STAT_3 => CHANNEL_STAT_14,
2681  m_axi_rx_tdata_3 => m_axi_rx_tdata_14,
2682  -- m_axi_rx_tkeep_3 => m_axi_rx_tkeep_3,
2683 -- m_axi_rx_tkeep_3 => open,
2684  m_axi_rx_tvalid_3 => m_axi_rx_tvalid_14,
2685  m_axi_rx_tlast_3 => m_axi_rx_tlast_14,
2686  -- User Flow Control RX Inteface
2687  m_axi_ufc_rx_tdata_3 => m_axi_ufc_rx_tdata_14(31 downto 0),
2688  m_axi_ufc_rx_tkeep_3 => open,
2689  m_axi_ufc_rx_tvalid_3 => m_axi_ufc_rx_tvalid_14,
2690  m_axi_ufc_rx_tlast_3 => m_axi_ufc_rx_tlast_14,
2691  USER_CLK_OUT_3 => user_clk_out_14,
2692 ------------------------------------------------
2693 
2694 
2695  RO_CTRL_TXN => RO_CTRL_TXN,
2696  RO_CTRL_TXP => RO_CTRL_TXP,
2697 
2698  DRP_CLK_IN => CLK_40,
2699  MASTER_RESET => MASTER_RESET,
2700  SW2 => gp_button_i,
2701 --EF DRP_CLK_IN_P : in std_logic;
2702 --EF DRP_CLK_IN_N : in std_logic;
2703 
2704 
2705 --Ports on the backplane block refer to Logical Slot mapping
2706 --slot 5 lane 1
2707 RXP_4 => RXP_4,
2708 RXN_4 => RXN_4,
2709 
2710 --RX_CHAN_UP_4 => open,
2711 --RX_HARD_ERR_4 => open,
2712 CHANNEL_CTRL_4 => CHANNEL_CTRL_8,
2713 CHANNEL_STAT_4 => CHANNEL_STAT_8,
2714 
2715 m_axi_rx_tdata_4 => m_axi_rx_tdata_8,
2716 -- m_axi_rx_tkeep_3 => m_axi_rx_tkeep_3,
2717 --m_axi_rx_tkeep_4 => open,
2718 m_axi_rx_tvalid_4 => m_axi_rx_tvalid_8,
2719 m_axi_rx_tlast_4 => m_axi_rx_tlast_8,
2720  -- User Flow Control RX Inteface
2721 m_axi_ufc_rx_tdata_4 => m_axi_ufc_rx_tdata_8(31 downto 0),
2722 m_axi_ufc_rx_tkeep_4 => open,
2723 m_axi_ufc_rx_tvalid_4 => m_axi_ufc_rx_tvalid_8,
2724 m_axi_ufc_rx_tlast_4 => m_axi_ufc_rx_tlast_8,
2725 USER_CLK_OUT_4 => user_clk_out_8,
2726 
2727 
2728 --Ports on the backplane block refer to Logical Slot mapping
2729 --slot 5 lane 2 (keep logical map for RXP/RXN)
2730 RXP_5 => RXP_5,
2731 RXN_5 => RXN_5,
2732 
2733 --RX_CHAN_UP_5 => open,
2734 --RX_HARD_ERR_5 => open,
2735 CHANNEL_CTRL_5 => CHANNEL_CTRL_9,
2736 CHANNEL_STAT_5 => CHANNEL_STAT_9,
2737 m_axi_rx_tdata_5 => m_axi_rx_tdata_9,
2738 -- m_axi_rx_tkeep_3 => m_axi_rx_tkeep_3,
2739 --m_axi_rx_tkeep_5 => open,
2740 m_axi_rx_tvalid_5 => m_axi_rx_tvalid_9,
2741 m_axi_rx_tlast_5 => m_axi_rx_tlast_9,
2742  -- User Flow Control RX Inteface
2743 m_axi_ufc_rx_tdata_5 => m_axi_ufc_rx_tdata_9(31 downto 0),
2744 m_axi_ufc_rx_tkeep_5 => open,
2745 m_axi_ufc_rx_tvalid_5 => m_axi_ufc_rx_tvalid_9,
2746 m_axi_ufc_rx_tlast_5 => m_axi_ufc_rx_tlast_9,
2747 USER_CLK_OUT_5 => user_clk_out_9,
2748 
2749 
2750 --Ports on the backplane block refer to Logical Slot mapping
2751 --slot 5 lane 3 (keep logical map for RXP/RXN)
2752 RXP_6 => RXP_6,
2753 RXN_6 => RXN_6,
2754 
2755 --RX_CHAN_UP_6 => open,
2756 --RX_HARD_ERR_6 => open,
2757 CHANNEL_CTRL_6 => CHANNEL_CTRL_11,
2758 CHANNEL_STAT_6 => CHANNEL_STAT_11,
2759 m_axi_rx_tdata_6 => m_axi_rx_tdata_11,
2760 -- m_axi_rx_tkeep_3 => m_axi_rx_tkeep_3,
2761 --m_axi_rx_tkeep_6 => open,
2762 m_axi_rx_tvalid_6 => m_axi_rx_tvalid_11,
2763 m_axi_rx_tlast_6 => m_axi_rx_tlast_11,
2764  -- User Flow Control RX Inteface
2765 m_axi_ufc_rx_tdata_6 => m_axi_ufc_rx_tdata_11(31 downto 0),
2766 m_axi_ufc_rx_tkeep_6 => open,
2767 m_axi_ufc_rx_tvalid_6 => m_axi_ufc_rx_tvalid_11,
2768 m_axi_ufc_rx_tlast_6 => m_axi_ufc_rx_tlast_11,
2769 USER_CLK_OUT_6 => user_clk_out_11,
2770 
2771 --Ports on the backplane block refer to Logical Slot mapping
2772 --slot 5 lane 4 (keep logical map for RXP/RXN)
2773 RXP_7 => RXP_7,
2774 RXN_7 => RXN_7,
2775 
2776 --RX_CHAN_UP_7 => open,
2777 --RX_HARD_ERR_7 => open,
2778 CHANNEL_CTRL_7 => CHANNEL_CTRL_10,
2779 CHANNEL_STAT_7 => CHANNEL_STAT_10,
2780 m_axi_rx_tdata_7 => m_axi_rx_tdata_10,
2781 -- m_axi_rx_tkeep_3 => m_axi_rx_tkeep_3,
2782 --m_axi_rx_tkeep_7 => open,
2783 m_axi_rx_tvalid_7 => m_axi_rx_tvalid_10,
2784 m_axi_rx_tlast_7 => m_axi_rx_tlast_10,
2785  -- User Flow Control RX Inteface
2786 m_axi_ufc_rx_tdata_7 => m_axi_ufc_rx_tdata_10(31 downto 0),
2787 m_axi_ufc_rx_tkeep_7 => open,
2788 m_axi_ufc_rx_tvalid_7 => m_axi_ufc_rx_tvalid_10,
2789 m_axi_ufc_rx_tlast_7 => m_axi_ufc_rx_tlast_10,
2790 USER_CLK_OUT_7 => user_clk_out_10,
2791 
2792  --Ports on the backplane block refer to Logical Slot mapping
2793 --slot 8 lane 1 (keep logical map for RXP/RXN)
2794 RXP_8 => RXP_8,
2795 RXN_8 => RXN_8,
2796 CHANNEL_CTRL_8 => CHANNEL_CTRL_16,
2797 CHANNEL_STAT_8 => CHANNEL_STAT_16,
2798 m_axi_rx_tdata_8 => m_axi_rx_tdata_16,
2799 m_axi_rx_tvalid_8 => m_axi_rx_tvalid_16,
2800 m_axi_rx_tlast_8 => m_axi_rx_tlast_16,
2801 m_axi_ufc_rx_tdata_8 => m_axi_ufc_rx_tdata_16(31 downto 0),
2802 m_axi_ufc_rx_tvalid_8 => m_axi_ufc_rx_tvalid_16,
2803 m_axi_ufc_rx_tlast_8 => m_axi_ufc_rx_tlast_16,
2804 USER_CLK_OUT_8 => user_clk_out_16,
2805 
2806 
2807 --Ports on the backplane block refer to Logical Slot mapping
2808 --slot 8 lane 2 (keep logical map for RXP/RXN)
2809 RXP_9 => RXP_9,
2810 RXN_9 => RXN_9,
2811 CHANNEL_CTRL_9 => CHANNEL_CTRL_17,
2812 CHANNEL_STAT_9 => CHANNEL_STAT_17,
2813 m_axi_rx_tdata_9 => m_axi_rx_tdata_17,
2814 m_axi_rx_tvalid_9 => m_axi_rx_tvalid_17,
2815 m_axi_rx_tlast_9 => m_axi_rx_tlast_17,
2816 m_axi_ufc_rx_tdata_9 => m_axi_ufc_rx_tdata_17(31 downto 0),
2817 m_axi_ufc_rx_tvalid_9 => m_axi_ufc_rx_tvalid_17,
2818 m_axi_ufc_rx_tlast_9 => m_axi_ufc_rx_tlast_17,
2819 USER_CLK_OUT_9 => user_clk_out_17,
2820 
2821 --Ports on the backplane block refer to Logical Slot mapping
2822 --slot 8 lane 3 (keep logical map for RXP/RXN)
2823 RXP_10 => RXP_10,
2824 RXN_10 => RXN_10,
2825 CHANNEL_CTRL_10 => CHANNEL_CTRL_19,
2826 CHANNEL_STAT_10 => CHANNEL_STAT_19,
2827 m_axi_rx_tdata_10 => m_axi_rx_tdata_19,
2828 m_axi_rx_tvalid_10 => m_axi_rx_tvalid_19,
2829 m_axi_rx_tlast_10 => m_axi_rx_tlast_19,
2830 m_axi_ufc_rx_tdata_10 => m_axi_ufc_rx_tdata_19(31 downto 0),
2831 m_axi_ufc_rx_tvalid_10 => m_axi_ufc_rx_tvalid_19,
2832 m_axi_ufc_rx_tlast_10 => m_axi_ufc_rx_tlast_19,
2833 USER_CLK_OUT_10 => user_clk_out_19,
2834 
2835 
2836 --Ports on the backplane block refer to Logical Slot mapping
2837 --slot 8 lane 4 (keep logical map for RXP/RXN)
2838 RXP_11 => RXP_11,
2839 RXN_11 => RXN_11,
2840 CHANNEL_CTRL_11 => CHANNEL_CTRL_18,
2841 CHANNEL_STAT_11 => CHANNEL_STAT_18,
2842 m_axi_rx_tdata_11 => m_axi_rx_tdata_18,
2843 m_axi_rx_tvalid_11 => m_axi_rx_tvalid_18,
2844 m_axi_rx_tlast_11 => m_axi_rx_tlast_18,
2845 m_axi_ufc_rx_tdata_11 => m_axi_ufc_rx_tdata_18(31 downto 0),
2846 m_axi_ufc_rx_tvalid_11 => m_axi_ufc_rx_tvalid_18,
2847 m_axi_ufc_rx_tlast_11 => m_axi_ufc_rx_tlast_18,
2848 USER_CLK_OUT_11 => user_clk_out_18,
2849 
2850 
2851 
2852 --Ports on the backplane block refer to Logical Slot mapping
2853 --slot 9 lane 1 (keep logical map for RXP/RXN)
2854 RXP_12 => RXP_12,
2855 RXN_12 => RXN_12,
2856 CHANNEL_CTRL_12 => CHANNEL_CTRL_4,
2857 CHANNEL_STAT_12 => CHANNEL_STAT_4,
2858 m_axi_rx_tdata_12 => m_axi_rx_tdata_4,
2859 m_axi_rx_tvalid_12 => m_axi_rx_tvalid_4,
2860 m_axi_rx_tlast_12 => m_axi_rx_tlast_4,
2861 m_axi_ufc_rx_tdata_12 => m_axi_ufc_rx_tdata_4(31 downto 0),
2862 m_axi_ufc_rx_tvalid_12 => m_axi_ufc_rx_tvalid_4,
2863 m_axi_ufc_rx_tlast_12 => m_axi_ufc_rx_tlast_4,
2864 USER_CLK_OUT_12 => user_clk_out_4,
2865 
2866 
2867 --Ports on the backplane block refer to Logical Slot mapping
2868 --slot 9 lane 2 (keep logical map for RXP/RXN)
2869 RXP_13 => RXP_13,
2870 RXN_13 => RXN_13,
2871 CHANNEL_CTRL_13 => CHANNEL_CTRL_5,
2872 CHANNEL_STAT_13 => CHANNEL_STAT_5,
2873 m_axi_rx_tdata_13 => m_axi_rx_tdata_5,
2874 m_axi_rx_tvalid_13 => m_axi_rx_tvalid_5,
2875 m_axi_rx_tlast_13 => m_axi_rx_tlast_5,
2876 m_axi_ufc_rx_tdata_13 => m_axi_ufc_rx_tdata_5(31 downto 0),
2877 m_axi_ufc_rx_tvalid_13 => m_axi_ufc_rx_tvalid_5,
2878 m_axi_ufc_rx_tlast_13 => m_axi_ufc_rx_tlast_5,
2879 USER_CLK_OUT_13 => user_clk_out_5,
2880 
2881 
2882 --Ports on the backplane block refer to Logical Slot mapping
2883 --slot 9 lane 3 (keep logical map for RXP/RXN)
2884 RXP_14 => RXP_14,
2885 RXN_14 => RXN_14,
2886 CHANNEL_CTRL_14 => CHANNEL_CTRL_7,
2887 CHANNEL_STAT_14 => CHANNEL_STAT_7,
2888 m_axi_rx_tdata_14 => m_axi_rx_tdata_7,
2889 m_axi_rx_tvalid_14 => m_axi_rx_tvalid_7,
2890 m_axi_rx_tlast_14 => m_axi_rx_tlast_7,
2891 m_axi_ufc_rx_tdata_14 => m_axi_ufc_rx_tdata_7(31 downto 0),
2892 m_axi_ufc_rx_tvalid_14 => m_axi_ufc_rx_tvalid_7,
2893 m_axi_ufc_rx_tlast_14 => m_axi_ufc_rx_tlast_7,
2894 USER_CLK_OUT_14 => user_clk_out_7,
2895 
2896 --Ports on the backplane block refer to Logical Slot mapping
2897 --slot 9 lane 4 (keep logical map for RXP/RXN)
2898 RXP_15 => RXP_15,
2899 RXN_15 => RXN_15,
2900 CHANNEL_CTRL_15 => CHANNEL_CTRL_6,
2901 CHANNEL_STAT_15 => CHANNEL_STAT_6,
2902 m_axi_rx_tdata_15 => m_axi_rx_tdata_6,
2903 m_axi_rx_tvalid_15 => m_axi_rx_tvalid_6,
2904 m_axi_rx_tlast_15 => m_axi_rx_tlast_6,
2905 m_axi_ufc_rx_tdata_15 => m_axi_ufc_rx_tdata_6(31 downto 0),
2906 m_axi_ufc_rx_tvalid_15 => m_axi_ufc_rx_tvalid_6,
2907 m_axi_ufc_rx_tlast_15 => m_axi_ufc_rx_tlast_6,
2908 USER_CLK_OUT_15 => user_clk_out_6,
2909 
2910 
2911 --Ports on the backplane block refer to Logical Slot mapping
2912 --slot 12 lane 1 (keep logical map for RXP/RXN)
2913 RXP_16 => RXP_16,
2914 RXN_16 => RXN_16,
2915 CHANNEL_CTRL_16 => CHANNEL_CTRL_20,
2916 CHANNEL_STAT_16 => CHANNEL_STAT_20,
2917 m_axi_rx_tdata_16 => m_axi_rx_tdata_20,
2918 m_axi_rx_tvalid_16 => m_axi_rx_tvalid_20,
2919 m_axi_rx_tlast_16 => m_axi_rx_tlast_20,
2920 m_axi_ufc_rx_tdata_16 => m_axi_ufc_rx_tdata_20(31 downto 0),
2921 m_axi_ufc_rx_tvalid_16 => m_axi_ufc_rx_tvalid_20,
2922 m_axi_ufc_rx_tlast_16 => m_axi_ufc_rx_tlast_20,
2923 USER_CLK_OUT_16 => user_clk_out_20,
2924 
2925 
2926 --Ports on the backplane block refer to Logical Slot mapping
2927 --slot 12 lane 2 (keep logical map for RXP/RXN)
2928 RXP_17 => RXP_17,
2929 RXN_17 => RXN_17,
2930 CHANNEL_CTRL_17 => CHANNEL_CTRL_21,
2931 CHANNEL_STAT_17 => CHANNEL_STAT_21,
2932 m_axi_rx_tdata_17 => m_axi_rx_tdata_21,
2933 m_axi_rx_tvalid_17 => m_axi_rx_tvalid_21,
2934 m_axi_rx_tlast_17 => m_axi_rx_tlast_21,
2935 m_axi_ufc_rx_tdata_17 => m_axi_ufc_rx_tdata_21(31 downto 0),
2936 m_axi_ufc_rx_tvalid_17 => m_axi_ufc_rx_tvalid_21,
2937 m_axi_ufc_rx_tlast_17 => m_axi_ufc_rx_tlast_21,
2938 USER_CLK_OUT_17 => user_clk_out_21,
2939 
2940 
2941 --Ports on the backplane block refer to Logical Slot mapping
2942 --slot 12 lane 3 (keep logical map for RXP/RXN)
2943 RXP_18 => RXP_18,
2944 RXN_18 => RXN_18,
2945 CHANNEL_CTRL_18 => CHANNEL_CTRL_23,
2946 CHANNEL_STAT_18 => CHANNEL_STAT_23,
2947 m_axi_rx_tdata_18 => m_axi_rx_tdata_23,
2948 m_axi_rx_tvalid_18 => m_axi_rx_tvalid_23,
2949 m_axi_rx_tlast_18 => m_axi_rx_tlast_23,
2950 m_axi_ufc_rx_tdata_18 => m_axi_ufc_rx_tdata_23(31 downto 0),
2951 m_axi_ufc_rx_tvalid_18 => m_axi_ufc_rx_tvalid_23,
2952 m_axi_ufc_rx_tlast_18 => m_axi_ufc_rx_tlast_23,
2953 USER_CLK_OUT_18 => user_clk_out_23,
2954 
2955 
2956 --Ports on the backplane block refer to Logical Slot mapping
2957 --slot 12 lane 4 (keep logical map for RXP/RXN)
2958 RXP_19 => RXP_19,
2959 RXN_19 => RXN_19,
2960 CHANNEL_CTRL_19 => CHANNEL_CTRL_22,
2961 CHANNEL_STAT_19 => CHANNEL_STAT_22,
2962 m_axi_rx_tdata_19 => m_axi_rx_tdata_22,
2963 m_axi_rx_tvalid_19 => m_axi_rx_tvalid_22,
2964 m_axi_rx_tlast_19 => m_axi_rx_tlast_22,
2965 m_axi_ufc_rx_tdata_19 => m_axi_ufc_rx_tdata_22(31 downto 0),
2966 m_axi_ufc_rx_tvalid_19 => m_axi_ufc_rx_tvalid_22,
2967 m_axi_ufc_rx_tlast_19 => m_axi_ufc_rx_tlast_22,
2968 USER_CLK_OUT_19 => user_clk_out_22,
2969 
2970 
2971 --Ports on the backplane block refer to Logical Slot mapping
2972 --slot 13 lane 1 (keep logical map for RXP/RXN)
2973 RXP_20 => RXP_20,
2974 RXN_20 => RXN_20,
2975 CHANNEL_CTRL_20 => CHANNEL_CTRL_0,
2976 CHANNEL_STAT_20 => CHANNEL_STAT_0,
2977 m_axi_rx_tdata_20 => m_axi_rx_tdata_0,
2978 m_axi_rx_tvalid_20 => m_axi_rx_tvalid_0,
2979 m_axi_rx_tlast_20 => m_axi_rx_tlast_0,
2980 m_axi_ufc_rx_tdata_20 => m_axi_ufc_rx_tdata_0(31 downto 0),
2981 m_axi_ufc_rx_tvalid_20 => m_axi_ufc_rx_tvalid_0,
2982 m_axi_ufc_rx_tlast_20 => m_axi_ufc_rx_tlast_0,
2983 USER_CLK_OUT_20 => user_clk_out_0,
2984 
2985 
2986 --Ports on the backplane block refer to Logical Slot mapping
2987 --slot 13 lane 2 (keep logical map for RXP/RXN)
2988 RXP_21 => RXP_21,
2989 RXN_21 => RXN_21,
2990 CHANNEL_CTRL_21 => CHANNEL_CTRL_1,
2991 CHANNEL_STAT_21 => CHANNEL_STAT_1,
2992 m_axi_rx_tdata_21 => m_axi_rx_tdata_1,
2993 m_axi_rx_tvalid_21 => m_axi_rx_tvalid_1,
2994 m_axi_rx_tlast_21 => m_axi_rx_tlast_1,
2995 m_axi_ufc_rx_tdata_21 => m_axi_ufc_rx_tdata_1(31 downto 0),
2996 m_axi_ufc_rx_tvalid_21 => m_axi_ufc_rx_tvalid_1,
2997 m_axi_ufc_rx_tlast_21 => m_axi_ufc_rx_tlast_1,
2998 USER_CLK_OUT_21 => user_clk_out_1,
2999 
3000 
3001 --Ports on the backplane block refer to Logical Slot mapping
3002 --slot 13 lane 3 (keep logical map for RXP/RXN)
3003 RXP_22 => RXP_22,
3004 RXN_22 => RXN_22,
3005 CHANNEL_CTRL_22 => CHANNEL_CTRL_3,
3006 CHANNEL_STAT_22 => CHANNEL_STAT_3,
3007 m_axi_rx_tdata_22 => m_axi_rx_tdata_3,
3008 m_axi_rx_tvalid_22 => m_axi_rx_tvalid_3,
3009 m_axi_rx_tlast_22 => m_axi_rx_tlast_3,
3010 m_axi_ufc_rx_tdata_22 => m_axi_ufc_rx_tdata_3(31 downto 0),
3011 m_axi_ufc_rx_tvalid_22 => m_axi_ufc_rx_tvalid_3,
3012 m_axi_ufc_rx_tlast_22 => m_axi_ufc_rx_tlast_3,
3013 USER_CLK_OUT_22 => user_clk_out_3,
3014 
3015 
3016 --Ports on the backplane block refer to Logical Slot mapping
3017 --slot 13 lane 4 (keep logical map for RXP/RXN)
3018 RXP_23 => RXP_23,
3019 RXN_23 => RXN_23,
3020 CHANNEL_CTRL_23 => CHANNEL_CTRL_2,
3021 CHANNEL_STAT_23 => CHANNEL_STAT_2,
3022 m_axi_rx_tdata_23 => m_axi_rx_tdata_2,
3023 m_axi_rx_tvalid_23 => m_axi_rx_tvalid_2,
3024 m_axi_rx_tlast_23 => m_axi_rx_tlast_2,
3025 m_axi_ufc_rx_tdata_23 => m_axi_ufc_rx_tdata_2(31 downto 0),
3026 m_axi_ufc_rx_tvalid_23 => m_axi_ufc_rx_tvalid_2,
3027 m_axi_ufc_rx_tlast_23 => m_axi_ufc_rx_tlast_2,
3028 USER_CLK_OUT_23 => user_clk_out_2,
3029 
3030 
3031 
3032 ----board tieoff signals
3033 -- CK_PWR_DNB : out std_logic;
3034 -- REF_CK_SEL : out std_logic;
3035 -- CK_SYNCB : out std_logic
3036 ----readout_ctrl specific
3037  ro_user_clock => ro_user_clock,
3038  ro_controller_reset => ro_controller_reset,
3039  ro_txcharisk => ro_txcharisk,
3040  ro_txdata => ro_txdata,
3041  ro_status => ro_status,
3042 
3043 
3044 
3045 --combined_TTC
3046  ttc_RXP => RXP_ttc,
3047  ttc_RXN => RXN_ttc,
3048  ttc_word_0 => ttc_word_0,
3049  ttc_word_1 => ttc_word_1,
3050  ttc_word_2 => ttc_word_2,
3051  ttc_word_3 => ttc_word_3,
3052  ttc_seq => ttc_seq,
3053  cttc_usrclk => cttc_usrclk,
3054  ttc_status => ttc_status,
3055  ttc_reset => ttc_reset,
3056 
3057  --------------------------ttc ports -----------------------------
3058  BP_CTTC_rxdata => BP_CTTC_rxdata,
3059  BP_CTTC_rxcharisk => BP_CTTC_rxcharisk,
3060  BP_CTTC_MGT_bus => BP_CTTC_MGT_bus,
3061  BP_CTTC_rxoutclk => BP_CTTC_rxoutclk
3062 
3063  );
3064 
3065 
3066 --CLK_axi_chan_0 : jfex_aurora_ila_clock_gen
3067 -- port map (
3068 -- clk_out1 => free_clk_out_0,
3069 -- clk_in1 => user_clk_out_0
3070 -- );
3071 ILA_axi_chan_0 : fex_rx_checker
3072  Port map (
3073  clock => user_clk_out_0, --user_clk_out_0,
3074  reset => backplane_control(1),
3075  tvalid => m_axi_rx_tvalid_0,
3076  tlast => m_axi_rx_tlast_0,
3077  tdata => m_axi_rx_tdata_0,
3078  channel_up => CHANNEL_STAT_0(0),
3079  soft_error => CHANNEL_STAT_0(9),
3080  hard_error => CHANNEL_STAT_0(8),
3081  L1A => L1A,
3082  l1id_mis_stretch => l1id_mis_stretch
3083  );
3084 
3085 
3086 
3087 
3088 
3089 
3090 --CLK_axi_chan_12 : jfex_aurora_ila_clock_gen
3091 -- port map (
3092 -- clk_out1 => free_clk_out_12,
3093 -- clk_in1 => user_clk_out_12
3094 -- );
3095 
3096 
3097 ILA_axi_chan_12 : fex_rx_checker
3098 
3099  Port map (
3100  clock => user_clk_out_12,
3101  reset => backplane_control(1),
3102  tvalid => m_axi_rx_tvalid_12,
3103  tlast => m_axi_rx_tlast_12,
3104  tdata => m_axi_rx_tdata_12,
3105  channel_up => CHANNEL_STAT_12(0),
3106  soft_error => CHANNEL_STAT_12(9),
3107  hard_error => CHANNEL_STAT_12(8),
3108  L1A => L1A,
3109  l1id_mis_stretch => l1id_mis_stretch
3110  );
3111 --ILA_axi_chan_12 : axi_ch0
3112 -- PORT MAP (
3113 -- clk => user_clk_out_12,
3114 -- probe0 => m_axi_rx_tdata_12,
3115 -- probe1(0) => m_axi_rx_tvalid_12,
3116 -- probe2(0) => m_axi_rx_tlast_12,
3117 -- probe3(0) => CHANNEL_STAT_12(0),
3118 -- probe4(0) => CHANNEL_STAT_12(12)
3119 -- );
3120 
3121 --CLK_axi_chan_13 : jfex_aurora_ila_clock_gen
3122 -- port map (
3123 -- clk_out1 => free_clk_out_13,
3124 -- clk_in1 => user_clk_out_13
3125 -- );
3126 
3127 ILA_axi_chan_13 : fex_rx_checker
3128  Port map (
3129  clock => user_clk_out_13,
3130  reset => backplane_control(1),
3131  tvalid => m_axi_rx_tvalid_13,
3132  tlast => m_axi_rx_tlast_13,
3133  tdata => m_axi_rx_tdata_13,
3134  channel_up => CHANNEL_STAT_13(0),
3135  soft_error => CHANNEL_STAT_13(9),
3136  hard_error => CHANNEL_STAT_13(8),
3137  L1A => L1A,
3138  l1id_mis_stretch => l1id_mis_stretch
3139  );
3140 
3141 --ILA_axi_chan_13 : axi_ch0
3142 -- PORT MAP (
3143 -- clk => user_clk_out_13,
3144 -- probe0 => m_axi_rx_tdata_13,
3145 -- probe1(0) => m_axi_rx_tvalid_13,
3146 -- probe2(0) => m_axi_rx_tlast_13,
3147 -- probe3(0) => CHANNEL_STAT_13(0),
3148 -- probe4(0) => CHANNEL_STAT_13(12)
3149 -- );
3150 
3151 --CLK_axi_chan_14 : jfex_aurora_ila_clock_gen
3152 -- port map (
3153 -- clk_out1 => free_clk_out_14,
3154 -- clk_in1 => user_clk_out_14
3155 -- );
3156 ILA_axi_chan_14 : fex_rx_checker
3157  Port map (
3158  clock => user_clk_out_14,
3159  reset => backplane_control(1),
3160 -- reset => channel_ctrl_14(0),
3161  tvalid => m_axi_rx_tvalid_14,
3162  tlast => m_axi_rx_tlast_14,
3163  tdata => m_axi_rx_tdata_14,
3164  channel_up => CHANNEL_STAT_14(0),
3165  soft_error => CHANNEL_STAT_14(9),
3166  hard_error => CHANNEL_STAT_14(8),
3167  L1A => L1A,
3168  l1id_mis_stretch => l1id_mis_stretch
3169  );
3170 
3171 
3172 --ILA_axi_chan_14 : axi_ch0
3173 -- PORT MAP (
3174 -- clk => user_clk_out_14,
3175 -- probe0 => m_axi_rx_tdata_14,
3176 -- probe1(0) => m_axi_rx_tvalid_14,
3177 -- probe2(0) => m_axi_rx_tlast_14,
3178 -- probe3(0) => CHANNEL_STAT_14(0),
3179 -- probe4(0) => CHANNEL_STAT_14(12)
3180 -- );
3181 
3182 --CLK_axi_chan_15 : jfex_aurora_ila_clock_gen
3183 -- port map (
3184 -- clk_out1 => free_clk_out_15,
3185 -- clk_in1 => user_clk_out_15
3186 -- );
3187 ILA_axi_chan_15 : fex_rx_checker
3188  Port map (
3189  clock => user_clk_out_15,
3190  reset => backplane_control(1),
3191  tvalid => m_axi_rx_tvalid_15,
3192  tlast => m_axi_rx_tlast_15,
3193  tdata => m_axi_rx_tdata_15,
3194  channel_up => CHANNEL_STAT_15(0),
3195  soft_error => CHANNEL_STAT_15(9),
3196  hard_error => CHANNEL_STAT_15(8),
3197  L1A => L1A,
3198  l1id_mis_stretch => l1id_mis_stretch
3199  );
3200 
3201 
3202 --ILA_axi_chan_15 : axi_ch0
3203 -- PORT MAP (
3204 -- clk => user_clk_out_15,
3205 -- probe0 => m_axi_rx_tdata_15,
3206 -- probe1(0) => m_axi_rx_tvalid_15,
3207 -- probe2(0) => m_axi_rx_tlast_15,
3208 -- probe3(0) => CHANNEL_STAT_15(0),
3209 -- probe4(0) => CHANNEL_STAT_15(12)
3210 -- );
3211 
3212 
3213 
3214 ILA_axi_chan_4 : axi_ch0
3215  PORT MAP (
3216  clk => user_clk_out_4,
3217  probe0 => m_axi_rx_tdata_4,
3218  probe1(0) => m_axi_rx_tvalid_4,
3219  probe2(0) => m_axi_rx_tlast_4,
3220  probe3(0) => CHANNEL_STAT_4(0),
3221  probe4(0) => CHANNEL_STAT_4(12)
3222  );
3223 
3224 
3225 ILA_axi_chan_5 : axi_ch0
3226  PORT MAP (
3227  clk => user_clk_out_5,
3228  probe0 => m_axi_rx_tdata_5,
3229  probe1(0) => m_axi_rx_tvalid_5,
3230  probe2(0) => m_axi_rx_tlast_5,
3231  probe3(0) => CHANNEL_STAT_5(0),
3232  probe4(0) => CHANNEL_STAT_5(12)
3233  );
3234 
3235 
3236 
3237 
3238 ILA_axi_chan_6 : axi_ch0
3239  PORT MAP (
3240  clk => user_clk_out_6,
3241  probe0 => m_axi_rx_tdata_6,
3242  probe1(0) => m_axi_rx_tvalid_6,
3243  probe2(0) => m_axi_rx_tlast_6,
3244  probe3(0) => CHANNEL_STAT_6(0),
3245  probe4(0) => CHANNEL_STAT_6(12)
3246  );
3247 
3248 ILA_axi_chan_7 : axi_ch0
3249  PORT MAP (
3250  clk => user_clk_out_7,
3251  probe0 => m_axi_rx_tdata_7,
3252  probe1(0) => m_axi_rx_tvalid_7,
3253  probe2(0) => m_axi_rx_tlast_7,
3254  probe3(0) => CHANNEL_STAT_7(0),
3255  probe4(0) => CHANNEL_STAT_7(12)
3256  );
3257 
3258 
3259 
3260 
3261 pp_ctrl_dbg: if debug=1 generate
3262 vio_pp_ctrl : pp_ctrl_vio
3263  PORT MAP (
3264  clk => pp_clock,
3265  probe_out0(23 downto 0) => channel_enable_vio(23 downto 0),
3266  probe_out1 => first_chan_vio,
3267  probe_out2 => last_chan_vio,
3268  probe_out3(0) => TTC_ignore_vio,
3269  probe_out4(0) => pp_soft_reset_vio,
3270  probe_out5(0) => debug_ctrl_vio
3271  );
3272 end generate pp_ctrl_dbg;
3273 
3274 pp_ctrl_wired: if debug=0 generate
3275 channel_enable_vio <= (others => '0');
3276 first_chan_vio <= (others => '0');
3277 last_chan_vio <= (others => '0');
3278 TTC_ignore_vio <= ('0');
3279 pp_soft_reset_vio <= ('0');
3280 debug_ctrl_vio <= ('0');
3281 end generate pp_ctrl_wired;
3282 -- pkt_areset <= not pkt_ARESETN;
3283 
3284 
3285 
3286 pp_reset <= sys_top_reset OR pp_soft_reset_vio;
3287 
3288  event_builder : packet_processor
3289  generic map (sim => 0,
3290  jfex => 1,
3291  CRC20_G_Poly => CRC20_G_Poly
3292  )
3293  port map (
3294  ipb_clk => ipb_clk,
3295  ipb_rst => ipb_rst,
3296 -- ipb_in => ipbw_backplane,
3297 -- ipb_out => ipbr_backplane,
3298 
3299  ipb_in_backplane => ipbw_backplane,
3300  ipb_out_backplane => ipbr_backplane,
3301 
3302  ipb_in_processor => ipbw_Processor,
3303  ipb_out_processor => ipbr_Processor,
3304 
3305  geo_location => geo_location,
3306  L1A => open,
3307  L1A_delay_out => L1A,
3308  l1id_mis_stretch => l1id_mis_stretch,
3309  full_mode_stat_tob_0 => full_mode_stat_tob_0,
3310  full_mode_stat_bulk_0 => full_mode_stat_bulk_0,
3311  full_mode_stat_bulk_1 => full_mode_stat_bulk_1,
3312  full_mode_stat_bulk_2 => full_mode_stat_bulk_2,
3313 
3314  FM_L1id_stat_tob_0 => FM_L1id_stat_tob_0,
3315  FM_L1id_stat_bulk_0 => FM_L1id_stat_bulk_0,
3316  FM_L1id_stat_bulk_1 => FM_L1id_stat_bulk_1,
3317  FM_L1id_stat_bulk_2 => FM_L1id_stat_bulk_2,
3318 
3319  full_mode_ctrl_tob_0 => full_mode_ctrl_tob_0,
3320  full_mode_ctrl_bulk_0 => full_mode_ctrl_bulk_0,
3321  full_mode_ctrl_bulk_1 => full_mode_ctrl_bulk_1,
3322  full_mode_ctrl_bulk_2 => full_mode_ctrl_bulk_2,
3323 
3324  stage_fifo_level_tob_0 => stage_fifo_level_tob_0(15 downto 0),
3325  stage_fifo_level_bulk_0 => stage_fifo_level_bulk_0(15 downto 0),
3326  stage_fifo_level_bulk_1 => stage_fifo_level_bulk_1(15 downto 0),
3327  stage_fifo_level_bulk_2 => stage_fifo_level_bulk_2(15 downto 0),
3328 
3329  stage_fifo_busy_tob_0 => stage_fifo_busy_tob_0,
3330  stage_fifo_xoff_tob_0 => open,
3331  stage_fifo_full_tob_0 => stage_fifo_full_tob_0,
3332  flx_backpressure_tob_0 => flx_backpressure_tob_0,
3333 
3334  stage_fifo_busy_bulk_0 => stage_fifo_busy_bulk_0,
3335  stage_fifo_xoff_bulk_0 => open,
3336  stage_fifo_full_bulk_0 => stage_fifo_full_bulk_0,
3337  flx_backpressure_bulk_0 => flx_backpressure_bulk_0,
3338 
3339  stage_fifo_busy_bulk_1 => stage_fifo_busy_bulk_1,
3340  stage_fifo_xoff_bulk_1 => open,
3341  stage_fifo_full_bulk_1 => stage_fifo_full_bulk_1,
3342  flx_backpressure_bulk_1 => flx_backpressure_bulk_1,
3343 
3344  stage_fifo_busy_bulk_2 => stage_fifo_busy_bulk_2,
3345  stage_fifo_xoff_bulk_2 => open,
3346  stage_fifo_full_bulk_2 => stage_fifo_full_bulk_2,
3347  flx_backpressure_bulk_2 => flx_backpressure_bulk_2,
3348 
3349  pp_clock => pp_clock,
3350  clk_40 => clk_40,
3351  clk_160 => clk_160,
3352 -- rt_clk => pp_clock,
3353  rt_clk => clk_40,
3354 
3355  backplane_control => backplane_control,
3356  init_clk => clk_125,
3357  master_reset => master_reset,
3358  rod_slot => geo_location(0),
3359  ck_pll_lock => ck_pll_lock,
3360 
3361  CK_INT => CK_INT,
3362  SMBALERT_B => SMBALERT_B,
3363  T_WRN_B => T_WRN_B,
3364 
3365  System_RESET => pp_reset,
3366  flx_backpressure => flx_bp_bus,
3367 
3368 --readout controller
3369  ro_user_clock => ro_user_clock,
3370  ro_controller_reset => ro_controller_reset,
3371  ro_txcharisk => ro_txcharisk,
3372  ro_txdata => ro_txdata,
3373  ro_status => ro_status,
3374 
3375 
3376 
3377 ------------------AURORA CLOCKS--------------
3378 -- user_clk_out_3 => needs to be added
3379  aurora_user_clock_0 => user_clk_out_0,
3380  aurora_user_clock_1 => user_clk_out_1,
3381  aurora_user_clock_2 => user_clk_out_2,
3382  aurora_user_clock_3 => user_clk_out_3,
3383  aurora_user_clock_4 => user_clk_out_4,
3384  aurora_user_clock_5 => user_clk_out_5,
3385  aurora_user_clock_6 => user_clk_out_6,
3386  aurora_user_clock_7 => user_clk_out_7,
3387  aurora_user_clock_8 => user_clk_out_8,
3388  aurora_user_clock_9 => user_clk_out_9,
3389  aurora_user_clock_10 => user_clk_out_10,
3390  aurora_user_clock_11 => user_clk_out_11,
3391  aurora_user_clock_12 => user_clk_out_12,
3392  aurora_user_clock_13 => user_clk_out_13,
3393  aurora_user_clock_14 => user_clk_out_14,
3394  aurora_user_clock_15 => user_clk_out_15,
3395  aurora_user_clock_16 => user_clk_out_16,
3396  aurora_user_clock_17 => user_clk_out_17,
3397  aurora_user_clock_18 => user_clk_out_18,
3398  aurora_user_clock_19 => user_clk_out_19,
3399  aurora_user_clock_20 => user_clk_out_20,
3400  aurora_user_clock_21 => user_clk_out_21,
3401  aurora_user_clock_22 => user_clk_out_22,
3402  aurora_user_clock_23 => user_clk_out_23,
3403 
3404 
3405 
3406  bp_data_0 => m_axi_rx_tdata_0,
3407  bp_data_1 => m_axi_rx_tdata_1,
3408  bp_data_2 => m_axi_rx_tdata_2,
3409  bp_data_3 => m_axi_rx_tdata_3,
3410  bp_data_4 => m_axi_rx_tdata_4,
3411  bp_data_5 => m_axi_rx_tdata_5,
3412  bp_data_6 => m_axi_rx_tdata_6,
3413  bp_data_7 => m_axi_rx_tdata_7,
3414  bp_data_8 => m_axi_rx_tdata_8,
3415  bp_data_9 => m_axi_rx_tdata_9,
3416  bp_data_10 => m_axi_rx_tdata_10,
3417  bp_data_11 => m_axi_rx_tdata_11,
3418  bp_data_12 => m_axi_rx_tdata_12,
3419  bp_data_13 => m_axi_rx_tdata_13,
3420  bp_data_14 => m_axi_rx_tdata_14,
3421  bp_data_15 => m_axi_rx_tdata_15,
3422  bp_data_16 => m_axi_rx_tdata_16,
3423  bp_data_17 => m_axi_rx_tdata_17,
3424  bp_data_18 => m_axi_rx_tdata_18,
3425  bp_data_19 => m_axi_rx_tdata_19,
3426  bp_data_20 => m_axi_rx_tdata_20,
3427  bp_data_21 => m_axi_rx_tdata_21,
3428  bp_data_22 => m_axi_rx_tdata_22,
3429  bp_data_23 => m_axi_rx_tdata_23,
3430 
3431  s_axis_tvalid_0 => m_axi_rx_tvalid_0,
3432  s_axis_tvalid_1 => m_axi_rx_tvalid_1,
3433  s_axis_tvalid_2 => m_axi_rx_tvalid_2,
3434  s_axis_tvalid_3 => m_axi_rx_tvalid_3,
3435  s_axis_tvalid_4 => m_axi_rx_tvalid_4,
3436  s_axis_tvalid_5 => m_axi_rx_tvalid_5,
3437  s_axis_tvalid_6 => m_axi_rx_tvalid_6,
3438  s_axis_tvalid_7 => m_axi_rx_tvalid_7,
3439  s_axis_tvalid_8 => m_axi_rx_tvalid_8,
3440  s_axis_tvalid_9 => m_axi_rx_tvalid_9,
3441  s_axis_tvalid_10 => m_axi_rx_tvalid_10,
3442  s_axis_tvalid_11 => m_axi_rx_tvalid_11,
3443  s_axis_tvalid_12 => m_axi_rx_tvalid_12,
3444  s_axis_tvalid_13 => m_axi_rx_tvalid_13,
3445  s_axis_tvalid_14 => m_axi_rx_tvalid_14,
3446  s_axis_tvalid_15 => m_axi_rx_tvalid_15,
3447  s_axis_tvalid_16 => m_axi_rx_tvalid_16,
3448  s_axis_tvalid_17 => m_axi_rx_tvalid_17,
3449  s_axis_tvalid_18 => m_axi_rx_tvalid_18,
3450  s_axis_tvalid_19 => m_axi_rx_tvalid_19,
3451  s_axis_tvalid_20 => m_axi_rx_tvalid_20,
3452  s_axis_tvalid_21 => m_axi_rx_tvalid_21,
3453  s_axis_tvalid_22 => m_axi_rx_tvalid_22,
3454  s_axis_tvalid_23 => m_axi_rx_tvalid_23,
3455 
3456 
3457  s_axis_tlast_0 => m_axi_rx_tlast_0,
3458  s_axis_tlast_1 => m_axi_rx_tlast_1,
3459  s_axis_tlast_2 => m_axi_rx_tlast_2,
3460  s_axis_tlast_3 => m_axi_rx_tlast_3,
3461  s_axis_tlast_4 => m_axi_rx_tlast_4,
3462  s_axis_tlast_5 => m_axi_rx_tlast_5,
3463  s_axis_tlast_6 => m_axi_rx_tlast_6,
3464  s_axis_tlast_7 => m_axi_rx_tlast_7,
3465  s_axis_tlast_8 => m_axi_rx_tlast_8,
3466  s_axis_tlast_9 => m_axi_rx_tlast_9,
3467  s_axis_tlast_10 => m_axi_rx_tlast_10,
3468  s_axis_tlast_11 => m_axi_rx_tlast_11,
3469  s_axis_tlast_12 => m_axi_rx_tlast_12,
3470  s_axis_tlast_13 => m_axi_rx_tlast_13,
3471  s_axis_tlast_14 => m_axi_rx_tlast_14,
3472  s_axis_tlast_15 => m_axi_rx_tlast_15,
3473  s_axis_tlast_16 => m_axi_rx_tlast_16,
3474  s_axis_tlast_17 => m_axi_rx_tlast_17,
3475  s_axis_tlast_18 => m_axi_rx_tlast_18,
3476  s_axis_tlast_19 => m_axi_rx_tlast_19,
3477  s_axis_tlast_20 => m_axi_rx_tlast_20,
3478  s_axis_tlast_21 => m_axi_rx_tlast_21,
3479  s_axis_tlast_22 => m_axi_rx_tlast_22,
3480  s_axis_tlast_23 => m_axi_rx_tlast_23,
3481 
3482  s_axi_ufc_rx_tdata_0 => m_axi_ufc_rx_tdata_0,
3483  s_axi_ufc_rx_tdata_1 => m_axi_ufc_rx_tdata_1,
3484  s_axi_ufc_rx_tdata_2 => m_axi_ufc_rx_tdata_2,
3485  s_axi_ufc_rx_tdata_3 => m_axi_ufc_rx_tdata_3,
3486  s_axi_ufc_rx_tdata_4 => m_axi_ufc_rx_tdata_4,
3487  s_axi_ufc_rx_tdata_5 => m_axi_ufc_rx_tdata_5,
3488  s_axi_ufc_rx_tdata_6 => m_axi_ufc_rx_tdata_6,
3489  s_axi_ufc_rx_tdata_7 => m_axi_ufc_rx_tdata_7,
3490  s_axi_ufc_rx_tdata_8 => m_axi_ufc_rx_tdata_8,
3491  s_axi_ufc_rx_tdata_9 => m_axi_ufc_rx_tdata_9,
3492  s_axi_ufc_rx_tdata_10 => m_axi_ufc_rx_tdata_10,
3493  s_axi_ufc_rx_tdata_11 => m_axi_ufc_rx_tdata_11,
3494  s_axi_ufc_rx_tdata_12 => m_axi_ufc_rx_tdata_12,
3495  s_axi_ufc_rx_tdata_13 => m_axi_ufc_rx_tdata_13,
3496  s_axi_ufc_rx_tdata_14 => m_axi_ufc_rx_tdata_14,
3497  s_axi_ufc_rx_tdata_15 => m_axi_ufc_rx_tdata_15,
3498  s_axi_ufc_rx_tdata_16 => m_axi_ufc_rx_tdata_16,
3499  s_axi_ufc_rx_tdata_17 => m_axi_ufc_rx_tdata_17,
3500  s_axi_ufc_rx_tdata_18 => m_axi_ufc_rx_tdata_18,
3501  s_axi_ufc_rx_tdata_19 => m_axi_ufc_rx_tdata_19,
3502  s_axi_ufc_rx_tdata_20 => m_axi_ufc_rx_tdata_20,
3503  s_axi_ufc_rx_tdata_21 => m_axi_ufc_rx_tdata_21,
3504  s_axi_ufc_rx_tdata_22 => m_axi_ufc_rx_tdata_22,
3505  s_axi_ufc_rx_tdata_23 => m_axi_ufc_rx_tdata_23,
3506 
3507 
3508 
3509  s_axi_ufc_rx_tvalid_0 => m_axi_ufc_rx_tvalid_0,
3510  s_axi_ufc_rx_tvalid_1 => m_axi_ufc_rx_tvalid_1,
3511  s_axi_ufc_rx_tvalid_2 => m_axi_ufc_rx_tvalid_2,
3512  s_axi_ufc_rx_tvalid_3 => m_axi_ufc_rx_tvalid_3,
3513  s_axi_ufc_rx_tvalid_4 => m_axi_ufc_rx_tvalid_4,
3514  s_axi_ufc_rx_tvalid_5 => m_axi_ufc_rx_tvalid_5,
3515  s_axi_ufc_rx_tvalid_6 => m_axi_ufc_rx_tvalid_6,
3516  s_axi_ufc_rx_tvalid_7 => m_axi_ufc_rx_tvalid_7,
3517  s_axi_ufc_rx_tvalid_8 => m_axi_ufc_rx_tvalid_8,
3518  s_axi_ufc_rx_tvalid_9 => m_axi_ufc_rx_tvalid_9,
3519  s_axi_ufc_rx_tvalid_10 => m_axi_ufc_rx_tvalid_10,
3520  s_axi_ufc_rx_tvalid_11 => m_axi_ufc_rx_tvalid_11,
3521  s_axi_ufc_rx_tvalid_12 => m_axi_ufc_rx_tvalid_12,
3522  s_axi_ufc_rx_tvalid_13 => m_axi_ufc_rx_tvalid_13,
3523  s_axi_ufc_rx_tvalid_14 => m_axi_ufc_rx_tvalid_14,
3524  s_axi_ufc_rx_tvalid_15 => m_axi_ufc_rx_tvalid_15,
3525  s_axi_ufc_rx_tvalid_16 => m_axi_ufc_rx_tvalid_16,
3526  s_axi_ufc_rx_tvalid_17 => m_axi_ufc_rx_tvalid_17,
3527  s_axi_ufc_rx_tvalid_18 => m_axi_ufc_rx_tvalid_18,
3528  s_axi_ufc_rx_tvalid_19 => m_axi_ufc_rx_tvalid_19,
3529  s_axi_ufc_rx_tvalid_20 => m_axi_ufc_rx_tvalid_20,
3530  s_axi_ufc_rx_tvalid_21 => m_axi_ufc_rx_tvalid_21,
3531  s_axi_ufc_rx_tvalid_22 => m_axi_ufc_rx_tvalid_22,
3532  s_axi_ufc_rx_tvalid_23 => m_axi_ufc_rx_tvalid_23,
3533 
3534 
3535 
3536  s_axi_ufc_rx_tlast_0 => m_axi_ufc_rx_tlast_0,
3537  s_axi_ufc_rx_tlast_1 => m_axi_ufc_rx_tlast_1,
3538  s_axi_ufc_rx_tlast_2 => m_axi_ufc_rx_tlast_2,
3539  s_axi_ufc_rx_tlast_3 => m_axi_ufc_rx_tlast_3,
3540  s_axi_ufc_rx_tlast_4 => m_axi_ufc_rx_tlast_4,
3541  s_axi_ufc_rx_tlast_5 => m_axi_ufc_rx_tlast_5,
3542  s_axi_ufc_rx_tlast_6 => m_axi_ufc_rx_tlast_6,
3543  s_axi_ufc_rx_tlast_7 => m_axi_ufc_rx_tlast_7,
3544  s_axi_ufc_rx_tlast_8 => m_axi_ufc_rx_tlast_8,
3545  s_axi_ufc_rx_tlast_9 => m_axi_ufc_rx_tlast_9,
3546  s_axi_ufc_rx_tlast_10 => m_axi_ufc_rx_tlast_10,
3547  s_axi_ufc_rx_tlast_11 => m_axi_ufc_rx_tlast_11,
3548  s_axi_ufc_rx_tlast_12 => m_axi_ufc_rx_tlast_12,
3549  s_axi_ufc_rx_tlast_13 => m_axi_ufc_rx_tlast_13,
3550  s_axi_ufc_rx_tlast_14 => m_axi_ufc_rx_tlast_14,
3551  s_axi_ufc_rx_tlast_15 => m_axi_ufc_rx_tlast_15,
3552  s_axi_ufc_rx_tlast_16 => m_axi_ufc_rx_tlast_16,
3553  s_axi_ufc_rx_tlast_17 => m_axi_ufc_rx_tlast_17,
3554  s_axi_ufc_rx_tlast_18 => m_axi_ufc_rx_tlast_18,
3555  s_axi_ufc_rx_tlast_19 => m_axi_ufc_rx_tlast_19,
3556  s_axi_ufc_rx_tlast_20 => m_axi_ufc_rx_tlast_20,
3557  s_axi_ufc_rx_tlast_21 => m_axi_ufc_rx_tlast_21,
3558  s_axi_ufc_rx_tlast_22 => m_axi_ufc_rx_tlast_22,
3559  s_axi_ufc_rx_tlast_23 => m_axi_ufc_rx_tlast_23,
3560 
3561 
3562  multichannel_busy => multichannel_busy,
3563  combined_busy => combined_busy,
3564 
3565 
3566 
3567 
3568 
3569  s_axis_tready_0 => open,
3570  s_axis_tready_1 => open,
3571  s_axis_tready_2 => open,
3572  s_axis_tready_3 => open,
3573  s_axis_tready_4 => open,
3574  s_axis_tready_5 => open,
3575  s_axis_tready_6 => open,
3576  s_axis_tready_7 => open,
3577  s_axis_tready_8 => open,
3578  s_axis_tready_9 => open,
3579  s_axis_tready_10 => open,
3580  s_axis_tready_11 => open,
3581  s_axis_tready_12 => open,
3582  s_axis_tready_13 => open,
3583  s_axis_tready_14 => open,
3584  s_axis_tready_15 => open,
3585  s_axis_tready_16 => open,
3586  s_axis_tready_17 => open,
3587  s_axis_tready_18 => open,
3588  s_axis_tready_19 => open,
3589  s_axis_tready_20 => open,
3590  s_axis_tready_21 => open,
3591  s_axis_tready_22 => open,
3592  s_axis_tready_23 => open,
3593 
3594 
3595 -- s_axis_tkeep_0 => m_axi_rx_tkeep_3,
3596 
3597 
3598  channel_enable_vio => channel_enable_vio,
3599  first_chan_vio => first_chan_vio,
3600  last_chan_vio => last_chan_vio,
3601  TTC_ignore_vio => TTC_ignore_vio,
3602  debug_ctrl_vio => debug_ctrl_vio,
3603 
3604 --- output queue(s)
3605 
3606  m_tvalid_0 => pp0_m_axi_tvalid,
3607  m_tlast_0 => pp0_m_axi_tlast,
3608  m_tdata_0 => pp0_m_axi_tdata,
3609  m_header_marker_0 => open,
3610  m_tail_marker_0 => open,
3611  m_tready_0 => pp0_m_axi_tready,
3612 
3613  bulk_m_tvalid_0 => bulk_m_tvalid_0,
3614  bulk_m_tlast_0 => bulk_m_tlast_0,
3615  bulk_m_tdata_0 => bulk_m_tdata_0,
3616  bulk_m_header_marker_0 => bulk_m_header_marker_0,
3617  bulk_m_tail_marker_0 => bulk_m_tail_marker_0,
3618  bulk_m_tready_0 => bulk_m_tready_0,
3619 
3620 
3621  bulk_m_tvalid_1 => bulk_m_tvalid_1,
3622  bulk_m_tlast_1 => bulk_m_tlast_1,
3623  bulk_m_tdata_1 => bulk_m_tdata_1,
3624  bulk_m_header_marker_1 => bulk_m_header_marker_1,
3625  bulk_m_tail_marker_1 => bulk_m_tail_marker_1,
3626  bulk_m_tready_1 => bulk_m_tready_1,
3627 
3628  bulk_m_tvalid_2 => bulk_m_tvalid_2,
3629  bulk_m_tlast_2 => bulk_m_tlast_2,
3630  bulk_m_tdata_2 => bulk_m_tdata_2,
3631  bulk_m_header_marker_2 => bulk_m_header_marker_2,
3632  bulk_m_tail_marker_2 => bulk_m_tail_marker_2,
3633  bulk_m_tready_2 => bulk_m_tready_2,
3634 
3635 
3636 --TTC signals
3637  cttc_user_clk => cttc_usrclk,
3638  ttc_status => ttc_status,
3639  ttc_reset => ttc_reset,
3640  hub_link_reset => hub_link_reset,
3641  ttc_seq => ttc_seq,
3642  ttc_word_0 => ttc_word_0,
3643  ttc_word_1 => ttc_word_1,
3644  ttc_word_2 => ttc_word_2,
3645  ttc_word_3 => ttc_word_3,
3646 
3647 
3648 --axi signals to register file
3649 
3650  aurora_chan_stat_0 => channel_stat_0,
3651  aurora_chan_stat_1 => channel_stat_1,
3652  aurora_chan_stat_2 => channel_stat_2,
3653  aurora_chan_stat_3 => channel_stat_3,
3654  aurora_chan_stat_4 => channel_stat_4,
3655  aurora_chan_stat_5 => channel_stat_5,
3656  aurora_chan_stat_6 => channel_stat_6,
3657  aurora_chan_stat_7 => channel_stat_7,
3658  aurora_chan_stat_8 => channel_stat_8,
3659  aurora_chan_stat_9 => channel_stat_9,
3660  aurora_chan_stat_10 => channel_stat_10,
3661  aurora_chan_stat_11 => channel_stat_11,
3662  aurora_chan_stat_12 => channel_stat_12,
3663  aurora_chan_stat_13 => channel_stat_13,
3664  aurora_chan_stat_14 => channel_stat_14,
3665  aurora_chan_stat_15 => channel_stat_15,
3666  aurora_chan_stat_16 => channel_stat_16,
3667  aurora_chan_stat_17 => channel_stat_17,
3668  aurora_chan_stat_18 => channel_stat_18,
3669  aurora_chan_stat_19 => channel_stat_19,
3670  aurora_chan_stat_20 => channel_stat_20,
3671  aurora_chan_stat_21 => channel_stat_21,
3672  aurora_chan_stat_22 => channel_stat_22,
3673  aurora_chan_stat_23 => channel_stat_23,
3674 
3675  aurora_chan_control_0 => channel_ctrl_0,
3676  aurora_chan_control_1 => channel_ctrl_1,
3677  aurora_chan_control_2 => channel_ctrl_2,
3678  aurora_chan_control_3 => channel_ctrl_3,
3679  aurora_chan_control_4 => channel_ctrl_4,
3680  aurora_chan_control_5 => channel_ctrl_5,
3681  aurora_chan_control_6 => channel_ctrl_6,
3682  aurora_chan_control_7 => channel_ctrl_7,
3683  aurora_chan_control_8 => channel_ctrl_8,
3684  aurora_chan_control_9 => channel_ctrl_9,
3685  aurora_chan_control_10 => channel_ctrl_10,
3686  aurora_chan_control_11 => channel_ctrl_11,
3687  aurora_chan_control_12 => channel_ctrl_12,
3688  aurora_chan_control_13 => channel_ctrl_13,
3689  aurora_chan_control_14 => channel_ctrl_14,
3690  aurora_chan_control_15 => channel_ctrl_15,
3691  aurora_chan_control_16 => channel_ctrl_16,
3692  aurora_chan_control_17 => channel_ctrl_17,
3693  aurora_chan_control_18 => channel_ctrl_18,
3694  aurora_chan_control_19 => channel_ctrl_19,
3695  aurora_chan_control_20 => channel_ctrl_20,
3696  aurora_chan_control_21 => channel_ctrl_21,
3697  aurora_chan_control_22 => channel_ctrl_22,
3698  aurora_chan_control_23 => channel_ctrl_23,
3699 
3700 
3701  ttc_mux_ctrl => ttc_mux_ctrl,
3702  BP_CTTC_rxdata => BP_CTTC_rxdata,
3703  FM_CTTC_rxdata => FM_CTTC_rxdata,
3704  BP_CTTC_rxcharisk => BP_CTTC_rxcharisk,
3705  FM_CTTC_rxcharisk => FM_CTTC_rxcharisk,
3706  BP_CTTC_MGT_bus => BP_CTTC_MGT_bus,
3707  FM_CTTC_MGT_bus => FM_CTTC_MGT_bus,
3708  BP_CTTC_rxoutclk => BP_CTTC_rxoutclk,
3709  FM_CTTC_rxoutclk => FM_CTTC_rxoutclk
3710  );
3711 
3712 ttc_source_sel : vio_ttc
3713  PORT MAP (
3714  clk => pp_clock,
3715  probe_in0(0) => '0',
3716  probe_out0(0) => ttc_mux_ctrl
3717  );
3718 
3719 
3720 --fm_soft_reset <= backplane_control(5) or backplane_control(6);
3721 fm_soft_reset <= backplane_control(6);
3722 
3723 fm_interface_1 : Full_Mode_Tx
3724  generic map ( debug => 0)
3725  port map (
3726  -- GTREFCLK0_N_IN => GTCLK_q218_c1n,
3727  -- GTREFCLK0_P_IN => GTCLK_q218_c1p,
3728  GTREFCLK0 => GTCLK_q218,
3729  pp_clock => pp_clock,
3730  RESET_BUTTON => '1',
3731 
3732  app_clk_in => CLK_40,
3733  gtrxn_in => "11",
3734  gtrxp_in => "00",
3735  gttxn_out => fm1_gttxn_out,
3736  gttxp_out => fm1_gttxp_out,
3737 
3738 
3739  s_axis_tvalid_0 => bulk_fm_tvalid_0,
3740  s_axis_tlast_0 => bulk_fm_tlast_0,
3741 
3742  --ready out from fm back to fifo connects to ready in on fifo
3743  s_axis_tready_0 => bulk_fm_tready_0,
3744  flx_bp_240_0 => flx_bp_240_bulk_0,
3745 
3746  s_axis_tdata_0 => bulk_fm_tdata_0,
3747  TXOUTCLK_0 => FM_TXOUTCLK,
3748  channel_reset_0 => master_reset,
3749  soft_reset_0 => fm_soft_reset,
3750  busy_0 => '0',
3751 -- TestMode_0 => '0',
3752  interface_reset_0 => FM1_reset_0,
3753  full_mode_ctrl_0 => full_mode_ctrl_bulk_0,
3754  full_mode_stat_0 => full_mode_stat_bulk_0,
3755  FM_L1id_stat_0 => FM_L1id_stat_bulk_0,
3756 
3757  s_axis_tvalid_1 => bulk_fm_tvalid_2,
3758  s_axis_tlast_1 => bulk_fm_tlast_2,
3759  s_axis_tready_1 => bulk_fm_tready_2,
3760  flx_bp_240_1 => flx_bp_240_bulk_2,
3761  s_axis_tdata_1 => bulk_fm_tdata_2,
3762  -- TXOUTCLK_1 : out std_logic;
3763  channel_reset_1 => master_reset,
3764  soft_reset_1 => fm_soft_reset,
3765  busy_1 => '0',
3766 -- TestMode_1 => '0',
3767  interface_reset_1 => FM1_reset_1,
3768  full_mode_ctrl_1 => full_mode_ctrl_bulk_2,
3769  full_mode_stat_1 => full_mode_stat_bulk_2,
3770  FM_L1id_stat_1 => FM_L1id_stat_bulk_2
3771 
3772  );
3773 
3774 normal_cttc: if alt_cttc=0 generate
3775 
3776  fm_interface_2 : Full_Mode_Tx
3777  generic map ( debug => 0)
3778  port map (
3779 
3780  GTREFCLK0 => GTCLK_q218,
3781  pp_clock => pp_clock,
3782  RESET_BUTTON => '1',
3783  app_clk_in => CLK_40,
3784  gtrxn_in => "11",
3785  gtrxp_in => "00",
3786  gttxn_out => fm2_gttxn_out,
3787  gttxp_out => fm2_gttxp_out,
3788  --
3789  --
3790  s_axis_tvalid_0 => bulk_fm_tvalid_1,
3791  s_axis_tlast_0 => bulk_fm_tlast_1,
3792  s_axis_tready_0 => bulk_fm_tready_1,
3793  flx_bp_240_0 => flx_bp_240_bulk_1,
3794  s_axis_tdata_0 => bulk_fm_tdata_1,
3795  TXOUTCLK_0 => FM_TXOUTCLK_2,
3796  channel_reset_0 => master_reset,
3797  soft_reset_0 => fm_soft_reset,
3798  busy_0 => '0',
3799  -- TestMode_0 => '0',
3800  interface_reset_0 => FM2_reset_0,
3801 
3802  full_mode_ctrl_0 => full_mode_ctrl_bulk_1,
3803  full_mode_stat_0 => full_mode_stat_bulk_1,
3804  FM_L1id_stat_0 => FM_L1id_stat_bulk_1,
3805 
3806  --
3807  s_axis_tvalid_1 => ppout_fifo_AXI4_TVALID,
3808  s_axis_tlast_1 => ppout_fifo_AXI4_TLAST,
3809  s_axis_tready_1 => felix_ch1_AXI4_TREADY,
3810  flx_bp_240_1 => flx_bp_240_tob_0,
3811  s_axis_tdata_1 => ppout_fifo_AXI4_TDATA,
3812  channel_reset_1 => master_reset,
3813  soft_reset_1 => fm_soft_reset,
3814  busy_1 => combined_busy,
3815 -- TestMode_1 => '0',
3816  interface_reset_1 => FM2_reset_1,
3817  full_mode_ctrl_1 => full_mode_ctrl_tob_0,
3818  full_mode_stat_1 => full_mode_stat_tob_0,
3819  FM_L1id_stat_1 => FM_L1id_stat_tob_0
3820  );
3821 
3822 end generate normal_cttc;
3823 
3824 
3825 
3826 alternate_cttc: if alt_cttc=1 generate
3827  fm_interface_3 : Full_Mode_CTTC
3828  generic map ( debug => 0)
3829  port map (
3830 
3831  GTREFCLK0 => GTCLK_q218,
3832  pp_clock => pp_clock,
3833  RESET_BUTTON => '1',
3834  app_clk_in => CLK_40,
3835 -- gtrxn_in => "11",
3836 -- gtrxp_in => "00",
3837  gttxn_out => fm2_gttxn_out,
3838  gttxp_out => fm2_gttxp_out,
3839  --
3840  --
3841  s_axis_tvalid_0 => bulk_fm_tvalid_1,
3842  s_axis_tlast_0 => bulk_fm_tlast_1,
3843  s_axis_tready_0 => bulk_fm_tready_1,
3844  flx_bp_240_0 => flx_bp_240_bulk_1,
3845  s_axis_tdata_0 => bulk_fm_tdata_1,
3846  TXOUTCLK_0 => FM_TXOUTCLK_2,
3847  channel_reset_0 => master_reset,
3848  soft_reset_0 => fm_soft_reset,
3849  busy_0 => '0',
3850  -- TestMode_0 => '0',
3851  interface_reset_0 => FM2_reset_0,
3852 
3853  full_mode_ctrl_0 => full_mode_ctrl_bulk_1,
3854  full_mode_stat_0 => full_mode_stat_bulk_1,
3855  FM_L1id_stat_0 => FM_L1id_stat_bulk_1,
3856 
3857  --
3858  s_axis_tvalid_1 => ppout_fifo_AXI4_TVALID,
3859  s_axis_tlast_1 => ppout_fifo_AXI4_TLAST,
3860  s_axis_tready_1 => felix_ch1_AXI4_TREADY,
3861  flx_bp_240_1 => flx_bp_240_tob_0,
3862  s_axis_tdata_1 => ppout_fifo_AXI4_TDATA,
3863  channel_reset_1 => master_reset,
3864  soft_reset_1 => fm_soft_reset,
3865  busy_1 => combined_busy,
3866 -- TestMode_1 => '0',
3867  interface_reset_1 => FM2_reset_1,
3868  full_mode_ctrl_1 => full_mode_ctrl_tob_0,
3869  full_mode_stat_1 => full_mode_stat_tob_0,
3870  FM_L1id_stat_1 => FM_L1id_stat_tob_0,
3871  ------CTTC connections -------
3872 --***** CTTC PORTS ***********************************
3873  gt_refclk_q219_c0 => gt_refclk_q219_c0,
3874  -- Q9_CLK0_GTREFCLK_IN_P => GTCLK_q219_c0p, --Q9_CLK0_GTREFCLK_IN_P,
3875  -- Q9_CLK0_GTREFCLK_IN_N => GTCLK_q219_c0n, --Q9_CLK0_GTREFCLK_IN_N,
3876  DRP_CLK_IN => clk_40,
3877  gt0_rxusrclk => open,
3878  TRACK_DATA_OUT => open,
3879  ttc_word_0 => open,
3880  ttc_word_1 => open,
3881  ttc_word_2 => open,
3882  ttc_word_3 => open,
3883  ttc_seq => open,
3884  ttc_status => open,
3885  ttc_reset => ttc_reset,
3886  sys_top_reset => sys_top_reset,
3887  stop_ttc_info => backplane_control(29),
3888 
3889 
3890  cttc_cpllreset_in => '0',
3891  gt0_cpllpd_in => '0',
3892  gt0_rxbufreset_in => '0',
3893  gt0_rxpcsreset_in => '0',
3894  gt0_rxpmareset_in => '0',
3895  gt0_rxcdrhold_in => '0',
3896  gt0_rxpd_in => '0',
3897 
3898  CTTC_RXN_IN => CTTC_rxn_alt,
3899  CTTC_RXP_IN => CTTC_rxp_alt,
3900 
3901  FM_CTTC_rxdata => FM_CTTC_rxdata,
3902  FM_CTTC_rxcharisk => FM_CTTC_rxcharisk,
3903  FM_CTTC_MGT_bus => FM_CTTC_MGT_bus,
3904  FM_CTTC_rxoutclk => FM_CTTC_rxoutclk
3905  );
3906 
3907 end generate alternate_cttc;
3908 
3909 combined_busy <= multichannel_busy or stage_fifo_busy_tob_0 or stage_fifo_busy_bulk_0 or stage_fifo_busy_bulk_1 or stage_fifo_busy_bulk_2;
3910 
3911 ---inverting lemo busy because tests were showing busy always active intil force bysy was set, bringing it inactive
3912 LEMO_i <= not combined_busy;
3913 --LEMO_i <= combined_busy;
3914 
3915 Bulk_0_64_32 : packet_fifo
3916  Port map (
3917  --Slave (input) side
3918  s_axis_tdata => bulk_m_tdata_0,
3919  s_axis_tvalid => bulk_m_tvalid_0,
3920  s_axis_tlast => bulk_m_tlast_0,
3921 -- s_axis_tdata => (others => '0'),
3922 -- s_axis_tvalid => '0',
3923 -- s_axis_tlast => '0',
3924 
3925 
3926 
3927 --ready output back to bulk processor
3928  s_axis_tready => bulk_m_tready_0,
3929 
3930  --Master (output) side
3931  m_axis_tdata => bulk_fm_tdata_0,
3932  m_axis_tvalid => bulk_fm_tvalid_0,
3933  m_axis_tready => bulk_fm_TREADY_0,
3934  m_axis_tlast => bulk_fm_tlast_0,
3935 
3936  --control
3937 -- DATA_COUNT => open,
3938  WR_DATA_COUNT => stage_fifo_level_bulk_0,
3939  RD_DATA_COUNT => open,
3940  fifo_full => stage_fifo_full_bulk_0,
3941  clk_160 => pp_clock,
3942 -- clk_160 => '0',
3943  clk_240 => FM_TXOUTCLK,
3944  RESET => FM1_reset_0,
3945 -- flx_backpressure => flx_bp_bus(bulk_0_flx_bp_link),
3946  flx_backpressure => flx_backpressure_bulk_0,
3947  flx_bp_enable => full_mode_ctrl_bulk_0(4),
3948  flx_bp_240 => flx_bp_240_bulk_0
3949 
3950  );
3951 
3952 Bulk_1_64_32 : packet_fifo
3953  Port map (
3954  --Slave (input) side
3955  s_axis_tdata => bulk_m_tdata_1,
3956  s_axis_tvalid => bulk_m_tvalid_1,
3957  s_axis_tlast => bulk_m_tlast_1,
3958 
3959 --ready output back to bulk processor
3960  s_axis_tready => bulk_m_tready_1,
3961 
3962  --Master (output) side
3963  m_axis_tdata => bulk_fm_tdata_1,
3964  m_axis_tvalid => bulk_fm_tvalid_1,
3965  m_axis_tready => bulk_fm_TREADY_1,
3966  m_axis_tlast => bulk_fm_tlast_1,
3967 
3968  --control
3969 -- DATA_COUNT => open,
3970  WR_DATA_COUNT => stage_fifo_level_bulk_1,
3971  RD_DATA_COUNT => open,
3972  fifo_full => stage_fifo_full_bulk_1,
3973  clk_160 => pp_clock,
3974 -- clk_160 => '0',
3975  clk_240 => FM_TXOUTCLK_2,
3976  RESET => FM2_reset_0,
3977 -- flx_backpressure => flx_bp_bus(bulk_1_flx_bp_link),
3978  flx_backpressure => flx_backpressure_bulk_1,
3979  flx_bp_enable => full_mode_ctrl_bulk_1(4),
3980  flx_bp_240 => flx_bp_240_bulk_1
3981 
3982  );
3983 
3984 Bulk_2_64_32 : packet_fifo
3985  Port map (
3986  --Slave (input) side
3987  s_axis_tdata => bulk_m_tdata_2,
3988  s_axis_tvalid => bulk_m_tvalid_2,
3989  s_axis_tlast => bulk_m_tlast_2,
3990 
3991 --ready output back to bulk processor
3992  s_axis_tready => bulk_m_tready_2,
3993 
3994  --Master (output) side
3995  m_axis_tdata => bulk_fm_tdata_2,
3996  m_axis_tvalid => bulk_fm_tvalid_2,
3997  m_axis_tready => bulk_fm_TREADY_2,
3998  m_axis_tlast => bulk_fm_tlast_2,
3999 
4000  --control
4001 -- DATA_COUNT => open,
4002  WR_DATA_COUNT => stage_fifo_level_bulk_2,
4003  RD_DATA_COUNT => open,
4004  fifo_full => stage_fifo_full_bulk_2,
4005  clk_160 => pp_clock,
4006 -- clk_160 => '0',
4007  clk_240 => FM_TXOUTCLK,
4008  RESET => FM1_reset_1,
4009 -- flx_backpressure => flx_bp_bus(bulk_2_flx_bp_link),
4010  flx_backpressure => flx_backpressure_bulk_2,
4011  flx_bp_enable => full_mode_ctrl_bulk_2(4),
4012  flx_bp_240 => flx_bp_240_bulk_2
4013 
4014  );
4015 
4016 
4017 
4018 
4019 
4020 
4021 
4022 
4023 
4024 pp_out_fifo_6432 : packet_fifo
4025  Port map (
4026  --Slave (input) side
4027  s_axis_tdata => pp0_m_axi_tdata,
4028  s_axis_tvalid => pp0_m_axi_tvalid,
4029  s_axis_tlast => pp0_m_axi_tlast,
4030  s_axis_tready => pp0_m_axi_tready,
4031 
4032  --Master (output) side
4033  m_axis_tdata => ppout_fifo_AXI4_TDATA,
4034  m_axis_tvalid => ppout_fifo_AXI4_TVALID,
4035  m_axis_tready => felix_ch1_AXI4_TREADY,
4036  m_axis_tlast => ppout_fifo_AXI4_tlast,
4037 
4038  --control
4039 -- DATA_COUNT => open,
4040  WR_DATA_COUNT => stage_fifo_level_tob_0,
4041  RD_DATA_COUNT => open,
4042  fifo_full => stage_fifo_full_tob_0,
4043  clk_160 => pp_clock,
4044  clk_240 => FM_TXOUTCLK_2,
4045  RESET => FM2_reset_1,
4046 -- flx_backpressure => flx_bp_bus(tob_0_flx_bp_link),
4047  flx_backpressure => flx_backpressure_tob_0,
4048  flx_bp_enable => full_mode_ctrl_tob_0(4),
4049  flx_bp_240 => flx_bp_240_tob_0
4050 
4051  );
4052 
4053 
4054 
4055 
4056 
4057 
4058 -- clk125_buf : IBUFG
4059  clk125_buf : IBUF
4060  port map (
4061  I => CLK_125_pin,
4062  O => CLK_125
4063  );
4064 
4065 --CLK40
4066  CLK_40_ibuf : IBUFDS
4067 -- CLK_40_ibuf : IBUFGDS
4068  port map
4069  (
4070  I => CLK_40_pin_P,
4071  IB => CLK_40_pin_N,
4072 -- O => CLK_40_pin
4073  O => CLK_40
4074  );
4075 
4076 -- CLK_40_g_buffer : BUFG
4077 -- port map
4078 -- (
4079 -- I => CLK_40_pin,
4080 -- O => CLK_40
4081 -- );
4082 
4083 
4084  spi_pwr: reset_count
4085  port map (
4086  clock => CLK_40,
4087  power_down_b => spi_pwr2
4088  );
4089 
4090 
4091  ck_pwr_dnb_buf : OBUF
4092  port map
4093  (
4094  I => spi_pwr2,
4095  O => CK_PWR_DNB
4096  );
4097 
4098 
4099  ck_spi_le_buf : OBUF
4100  port map
4101  (
4102  I => '1',
4103  O => CK_SPI_LE
4104 
4105  );
4106 
4107 
4108 
4109 
4110 
4111 
4112 
4113 -- ck_pwr_dnb_buf : OBUF
4114 -- port map
4115 -- (
4116 -- I => '1',
4117 -- O => CK_PWR_DNB
4118 -- );
4119 
4120  ref_ck_sel_buf : OBUF
4121  port map
4122  (
4123  I => '1',
4124  O => REF_CLK_SEL
4125  );
4126 
4127  ck_syncb_buf : OBUF
4128  port map
4129  (
4130  I => '1',
4131  O => CK_SYNCB
4132  );
4133 
4134  pwr_con3_buf : OBUF
4135  port map
4136  (
4137  I => '1',
4138  O => PWR_CON3
4139  );
4140 
4141  pwr_con4_buf : OBUF
4142  port map
4143  (
4144  -- I => hub_reset,
4145  I => sys_top_reset,
4146  O => PWR_CON4
4147  );
4148 
4149 
4150  ibufds_q218 : IBUFDS_GTE2
4151  port map
4152  (
4153  O => GTCLK_q218,
4154  ODIV2 => open,
4155  CEB => '0',
4156  I => GTCLK_q218_c1p,
4157  IB => GTCLK_q218_c1n
4158  );
4159 
4160 
4161 
4162 --GP button test
4163  button_ibuf : IBUF
4164  port map (
4165  I => gp_button,
4166  O => gp_button_ibuf
4167  );
4168 
4169 --gp_button_i <= not (not gp_button_ibuf or vio_reset);
4170  gp_button_i <= not (not gp_button_ibuf or vio_reset or backplane_control(0));
4171 
4172  LEMO_obuf : OBUF
4173  port map
4174  (
4175  I => lemo_i,
4176  O => LEMO
4177  );
4178 
4179 
4180  IBUFDS_GTE2_q219_c0 : IBUFDS_GTE2
4181  port map (
4182  I => GTCLK_q219_c0p,
4183  IB => GTCLK_q219_c0n,
4184  CEB => '0',
4185  O => gt_refclk_q219_c0,
4186  ODIV2 => OPEN);
4187 
4188 
4189 
4190 bkpln_cntl_dbg: if debug=1 generate
4191 bkpln_control_ila : backplane_control_ila
4192 PORT MAP (
4193  clk => user_clk_out_5,
4194  probe0 => backplane_control
4195 );
4196 end generate bkpln_cntl_dbg;
4197 
4198 end RTL;
4199 
4200 
4201 
4202 
4203 
4204 
fex_rx_checker
Definition: fex_rx_checker.vhd:34
packet_fifo
Definition: packet_fifo.vhd:36
packet_processor
Definition: packet_processor.vhd:44
reset_count
Definition: reset_count.vhd:35
system_top_reset
Reset Timer.
Definition: system_top_reset.vhd:9
top_rod_jfex.rtl
Definition: top_rod_jfex.vhd:386
top_rod_jfex
Definition: top_rod_jfex.vhd:46
top_rod_jfex.GLOBAL_VER
GLOBAL_VER std_logic_vector( 31 downto 0) := x"00000002"
Version of the repository (format: MMmmcccc in hex)
Definition: top_rod_jfex.vhd:65
top_rod_jfex.GLOBAL_TIME
GLOBAL_TIME std_logic_vector( 31 downto 0) := x"00000001"
Time format 00HHMMSS in decimal.
Definition: top_rod_jfex.vhd:63
top_rod_jfex.TOP_VER
TOP_VER std_logic_vector( 31 downto 0) := x"00000004"
Version of the top folder, see TOP_SHA.
Definition: top_rod_jfex.vhd:69
top_rod_jfex.GLOBAL_DATE
GLOBAL_DATE std_logic_vector( 31 downto 0) := x"20230001"
Date format DDMMYYYY in decimal.
Definition: top_rod_jfex.vhd:61
top_rod_jfex.CON_SHA
CON_SHA std_logic_vector( 31 downto 0) := x"00000007"
Short 7-digit git SHA of the Hog submodule.
Definition: top_rod_jfex.vhd:74
top_rod_jfex.HOG_SHA
HOG_SHA std_logic_vector( 31 downto 0) := x"00000009"
Short 7-digit git SHA of the Hog submodule.
Definition: top_rod_jfex.vhd:77
top_rod_jfex.XML_SHA
XML_SHA std_logic_vector( 31 downto 0) := x"0000000a"
Short 7-digit git SHA of the XMLs.
Definition: top_rod_jfex.vhd:81
top_rod_jfex.XML_VER
XML_VER std_logic_vector( 31 downto 0) := x"0000000b"
Version of the XMLs.
Definition: top_rod_jfex.vhd:83
top_rod_jfex.TOP_SHA
TOP_SHA std_logic_vector( 31 downto 0) := x"00000005"
Short 7-digit git SHA of the top folder: list file, xdcs, XMLs, tcl file and this file.
Definition: top_rod_jfex.vhd:71
top_rod_jfex.GLOBAL_SHA
GLOBAL_SHA std_logic_vector( 31 downto 0) := x"00000003"
Short 7-digit git SHA of the repository.
Definition: top_rod_jfex.vhd:67
Generated on Sat Dec 14 2024 13:33:14 for ROD firmware by   doxygen 1.9.1