watchdog Entity Reference

Inheritance diagram for watchdog:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
STD_LOGIC_UNSIGNED

Generics
overflow_clock_count	std_logic_vector ( 7 downto 0 ) := x " 0f "
counter_width	integer := 19
msb	integer := ( counter_width- 1 )
lsb	integer := ( counter_width- 16 )

Ports
pp_clock	in	STD_LOGIC
reset_in	in	STD_LOGIC
wdog_disable	in	STD_LOGIC
wdog_pet	in	STD_LOGIC
wdog_threshold	in	STD_LOGIC_VECTOR ( 15 downto 0 )
wdog_overflow	out	STD_LOGIC

Detailed Description

Definition at line 33 of file watchdog.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/watchdog.vhd