watchdog.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 20.08.2021 14:53:17
-- Design Name: 
-- Module Name: watchdog - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--  
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity watchdog is
    generic ( 
          overflow_clock_count : std_logic_vector(7 downto 0) := x"0f";
          counter_width                  :  integer    := 19;
          msb                            :  integer    := (counter_width - 1);
          lsb                            :  integer    := (counter_width - 16)    
          );
    Port ( pp_clock         : in STD_LOGIC;
           reset_in         : in STD_LOGIC;
           wdog_disable     : in STD_LOGIC;
           wdog_pet         : in STD_LOGIC;
           wdog_threshold   : in STD_LOGIC_VECTOR (15 downto 0);
           wdog_overflow    : out STD_LOGIC);
end watchdog;
 
architecture RTL of watchdog is
 
signal  wd_counter   : std_logic_vector(msb downto 0) := (others => '0');
signal  overflow_i   : std_logic := '0';
signal  output_timer : std_logic_vector(7 downto 0) := x"00";
signal  wdog_overflow_i : std_logic;
 
begin
 
process (pp_clock) begin
  if rising_edge (pp_clock) then
   if (reset_in = '1') or (overflow_i = '1') or (wdog_pet = '1') or (wdog_disable = '1') then
       wd_counter <= (others => '0');
   else wd_counter <= wd_counter + '1';
   end if;
 end if; 
end process;    
       
process (pp_clock) begin
  if rising_edge (pp_clock) then
    if wd_counter(msb downto lsb) = wdog_threshold then
      overflow_i <= '1';
    else 
      overflow_i <= '0'; 
    end if; 
  end if;     
end process;
 
--wdog_overflow <= overflow_i;
process (pp_clock) begin
  if rising_edge (pp_clock) then
--    if (reset_in = '1' or wdog_disable = '1') then
    if (wdog_disable = '1') then  
        output_timer <= x"00"; 
    elsif (overflow_i = '1') then
        output_timer <= overflow_clock_count; 
    elsif (output_timer /= x"00") then
        output_timer <= (output_timer - '1');
    else 
        output_timer <= x"00";
    end if;          
   end if;
 end process;   
 
wdog_overflow_i <= OR (output_timer);
wdog_overflow <=  wdog_overflow_i;
end RTL;