AlgoCore_eg.vhd File Reference

Core of the electromagnetic algorithm. More...

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Entities
AlgoCore_eg	entity
	Core of the electromagnetic algorithm. More...
Behavioral	architecture
	Core of the electromagnetic algorithm. More...

Detailed Description

Core of the electromagnetic algorithm.

The total latency of this block is 10 clock cycles, this is a table representing the timing:

clock cycle	0	1	2	3	4	5	6	7	8	9	10
RAM address	0	1	2	3	4	0	1	2	3	4	0
seed finder	X	X
In mux	X	X
Adders env			X	X	X	X
Addders core			X	X	X	X	X	X	X
Multipliers							X	X	X
Seed delay			X	X	X	X	X	X	X	X	X
TOB energy										X	X
Threshold delay						X	X	X
Conditions										X	X
Dead Mat. Corr.			X
DMC delay	X	X

At clock cycle 0 the data is provided to the algorithm.

At clock cycle 1, the seed is ready and so is the data coming out of the input multiplexer, which is provided to the adders.

At clock cycle 5, the envoronment sums are ready and fed into the multipliers.

At clock cycle 8, all the sums and the multiplications are done and the valued are fed into the conditions

At clock cycle 8 also the energy threshold is applied.

At clock cycle 10 the TOBs are formed with the conditions bits and the Energy

The parameters used to evaluate the conditions are read from the RAM at clock cycle 0 or 5 (the RAM address goes form 0 to 4).

A delay of 2 clock cycles is used to pipeline the correct value for Dead Materal Correction (DMC) parameters that are read at clock cycle 2, i.e. when data is provided to the adders.

A delay of 3 clock cycles is used to delay the energy thresholds which are read at clock cycle 8, i.e. when the conditions are evaluated.

Author

Francesco Gonnella

Definition in file AlgoCore_eg.vhd.