Behavioral Architecture Reference

Core of the electromagnetic algorithm. More...

Processes
CONDITIONS	( CLK200 )

Signals
ParREta	AlgoParameters ( 2 downto 0 )
ParWs	AlgoParameters ( 2 downto 0 )
ParRh	AlgoParameters ( 2 downto 0 )
SF_Data	DataWords ( 5 downto 0 )
SF_DataUp	DataWords ( 5 downto 0 )
SF_DataDown	DataWords ( 5 downto 0 )
SF_UpNotDown	std_logic
SF_Seed	std_logic_vector ( 1 downto 0 )
SF_IsLocalMax	std_logic
SF_IsMax	std_logic
IM_Towers	TriggerTowers ( 8 downto 0 )
IM_EnergyL0	DataWords ( 1 downto 0 )
Corrected_EnergyL0	DataWords ( 13 downto 0 )
Corrected_EnergyL3	DataWords ( 13 downto 0 )
Corrected_EnergyL1	DataWords ( 41 downto 0 )
Corrected_EnergyL2	DataWords ( 41 downto 0 )
IM_EnergyL1	DataWords ( 5 downto 0 )
IM_EnergyL2	DataWords ( 5 downto 0 )
IM_EnergyL3	DataWords ( 1 downto 0 )
IM_REtaCoreData	DataWords ( 5 downto 0 )
IM_REtaEnvData	DataWords ( 14 downto 0 )
IM_WsCoreData	DataWords ( 11 downto 0 )
IM_WsEnvData	DataWords ( 14 downto 0 )
IM_HadEnvDataL1	DataWords ( 5 downto 0 )
IM_HadEnvDataL2	DataWords ( 5 downto 0 )
IM_HadEnvDataL03	DataWords ( 1 downto 0 )
IM_HadCoreData	DataWords ( 17 downto 0 )
MA_EnergyOverflow	std_logic
MA_EnergySum	DataWord
MA_REtaEnvOverflow	std_logic
MA_REtaEnvSum	DataWord
MA_REtaCoreOverflow	std_logic
MA_REtaCoreSum	DataWord
MA_WsEnvOverflow	std_logic
MA_WsEnvSum	DataWord
MA_WsCoreOverflow	std_logic
MA_WsCoreSum	DataWord
MA_HadCoreOverflow	std_logic
MA_HadCoreSum	DataWord
MA_HadEnvOverflow	std_logic
MA_HadEnvSum	DataWord
MU_REtaEnvOverflows	std_logic_vector ( 2 downto 0 )
MU_WsCoreOverflows	std_logic_vector ( 2 downto 0 )
MU_HadCoreOverflows	std_logic_vector ( 2 downto 0 )
MU_REtaEnvMult	DataWords ( 2 downto 0 )
MU_WsCoreMult	DataWords ( 2 downto 0 )
MU_HadCoreMult	DataWords ( 2 downto 0 )
DL_SeedFinder	std_logic_vector ( 4 downto 0 )
DL_UpNotDown	std_logic
DL_Seed	std_logic_vector ( 1 downto 0 )
DL_IsLocalMax	std_logic
DL_IsMax	std_logic
DL_Overflows	std_logic_vector ( 2 downto 0 )
DL_REtaEnvOverflow	std_logic
DL_WsCoreOverflow	std_logic
DL_HadCoreOverflow	std_logic
REtaCondition	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
WsCondition	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
HadCondition	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
TOBEnergy	DataWord := ( others = > ' 0 ' )
TOBEnergyOverflow	std_logic := ' 0 '
ConditionThr	DataWord
ConditionThr_d	DataWord
EnergyThr	DataWord
EnergyThr_d	DataWord
DMC_b0_mask	std_logic_vector ( 6 downto 0 )
DMC_b1_mask	std_logic_vector ( 6 downto 0 )
DMC_b2_mask	std_logic_vector ( 6 downto 0 )
DMC_b3_mask	std_logic_vector ( 6 downto 0 )
max_enable	std_logic

Instantiations
seed_finder	SeedFinder <Entity SeedFinder>
input_multiplexer	egInputMultiplexer <Entity egInputMultiplexer>
dead_material_delay	GeneralDelay <Entity GeneralDelay>
multi_adder_energy	MultiAdder <Entity MultiAdder>
multi_adder_reta_env	MultiAdder <Entity MultiAdder>
multi_adder_reta_core	MultiAdder <Entity MultiAdder>
multi_adder_ws_core	MultiAdder <Entity MultiAdder>
multi_adder_ws_env	MultiAdder <Entity MultiAdder>
multi_adder_had_core	MultiAdder <Entity MultiAdder>
multi_adder_had_env	MultiAdder <Entity MultiAdder>
reta_multiplier	MultiMultiplier <Entity MultiMultiplier>
ws_multiplier	MultiMultiplier <Entity MultiMultiplier>
hadron_multiplier	MultiMultiplier <Entity MultiMultiplier>
condition_threshold_delay	Delay <Entity Delay>
energy_threshold_delay	Delay <Entity Delay>
seed_delay	GeneralDelay <Entity GeneralDelay>
overflow_delay	GeneralDelay <Entity GeneralDelay>

Detailed Description

Core of the electromagnetic algorithm.

The total latency of this block is 10 clock cycles, this is a table representing the timing:

clock cycle	0	1	2	3	4	5	6	7	8	9	10
RAM address	0	1	2	3	4	0	1	2	3	4	0
seed finder	X	X
In mux	X	X
Adders env			X	X	X	X
Addders core			X	X	X	X	X	X	X
Multipliers							X	X	X
Seed delay			X	X	X	X	X	X	X	X	X
TOB energy										X	X
Threshold delay						X	X	X
Conditions										X	X
Dead Mat. Corr.			X
DMC delay	X	X

At clock cycle 0 the data is provided to the algorithm.

At clock cycle 1, the seed is ready and so is the data coming out of the input multiplexer, which is provided to the adders.

At clock cycle 5, the envoronment sums are ready and fed into the multipliers.

At clock cycle 8, all the sums and the multiplications are done and the valued are fed into the conditions

At clock cycle 8 also the energy threshold is applied.

At clock cycle 10 the TOBs are formed with the conditions bits and the Energy

The parameters used to evaluate the conditions are read from the RAM at clock cycle 0 or 5 (the RAM address goes form 0 to 4).

A delay of 2 clock cycles is used to pipeline the correct value for Dead Materal Correction (DMC) parameters that are read at clock cycle 2, i.e. when data is provided to the adders.

A delay of 3 clock cycles is used to delay the energy thresholds which are read at clock cycle 8, i.e. when the conditions are evaluated.

Author

Francesco Gonnella

Definition at line 75 of file AlgoCore_eg.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/AlgoCore_eg.vhd