AlgoCore_eg.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
use work.DataTypes.all;
 
library infrastructure_lib;
 
entity AlgoCore_eg is
  generic(
  EG_ALGO_VERSION : std_logic_vector(1 downto 0)
  );
  port (CLK200 : in std_logic;
 
        IN_ParWs     : in AlgoParameters(2 downto 0);
        IN_ParREta   : in AlgoParameters(2 downto 0);
        IN_ParHadron : in AlgoParameters(2 downto 0);
        IN_glob_Position : in  AlgoRegister := (others => '0');
 
        IN_ParDeadMat_b0 : in AlgoParameter;
        IN_ParDeadMat_b1 : in AlgoParameter;
        IN_ParDeadMat_b2 : in AlgoParameter;
        IN_ParDeadMat_b3 : in AlgoParameter;                
 
        IN_Energy_threshold : in DataWord;
        IN_Cond_threshold   : in DataWord;
 
        IN_Data : in TriggerTowers(8 downto 0);
 
        OUT_TOB : out TriggerObject_eg);
end AlgoCore_eg;
 
architecture Behavioral of AlgoCore_eg is
 
  signal ParREta : AlgoParameters(2 downto 0);
  signal ParWs   : AlgoParameters(2 downto 0);
  signal ParRh   : AlgoParameters(2 downto 0);
 
-- Seed Finder
  signal SF_Data       : DataWords(5 downto 0);
  signal SF_DataUp     : DataWords(5 downto 0);
  signal SF_DataDown   : DataWords(5 downto 0);
  signal SF_UpNotDown  : std_logic;
  signal SF_Seed       : std_logic_vector(1 downto 0);
  signal SF_IsLocalMax : std_logic;
  signal SF_IsMax      : std_logic;
 
-- Input Multiplexer
  signal IM_Towers          : TriggerTowers(8 downto 0);
  signal IM_EnergyL0        : DataWords(1 downto 0);
  signal Corrected_EnergyL0 : DataWords(13 downto 0);
  signal Corrected_EnergyL3 : DataWords(13 downto 0);
  signal Corrected_EnergyL1 : DataWords(41 downto 0);
  signal Corrected_EnergyL2 : DataWords(41 downto 0);
 
  signal IM_EnergyL1      : DataWords(5 downto 0);
  signal IM_EnergyL2      : DataWords(5 downto 0);
  signal IM_EnergyL3      : DataWords(1 downto 0);
  signal IM_REtaCoreData  : DataWords(5 downto 0);
  signal IM_REtaEnvData   : DataWords(14 downto 0);
  signal IM_WsCoreData    : DataWords(11 downto 0);
  signal IM_WsEnvData     : DataWords(14 downto 0);
  signal IM_HadEnvDataL1  : DataWords(5 downto 0);
  signal IM_HadEnvDataL2  : DataWords(5 downto 0);
  signal IM_HadEnvDataL03 : DataWords(1 downto 0);
  signal IM_HadCoreData   : DataWords(17 downto 0);
 
-- Multi Adders
  signal MA_EnergyOverflow : std_logic;
  signal MA_EnergySum      : DataWord;
 
  signal MA_REtaEnvOverflow  : std_logic;
  signal MA_REtaEnvSum       : DataWord;
  signal MA_REtaCoreOverflow : std_logic;
  signal MA_REtaCoreSum      : DataWord;
 
  signal MA_WsEnvOverflow  : std_logic;
  signal MA_WsEnvSum       : DataWord;
  signal MA_WsCoreOverflow : std_logic;
  signal MA_WsCoreSum      : DataWord;
 
  signal MA_HadCoreOverflow : std_logic;
  signal MA_HadCoreSum      : DataWord;
  signal MA_HadEnvOverflow  : std_logic;
  signal MA_HadEnvSum       : DataWord;
 
-- Multipliers
  signal MU_REtaEnvOverflows : std_logic_vector(2 downto 0);
  signal MU_WsCoreOverflows  : std_logic_vector(2 downto 0);
  signal MU_HadCoreOverflows : std_logic_vector(2 downto 0);
 
  signal MU_REtaEnvMult : DataWords(2 downto 0);
  signal MU_WsCoreMult  : DataWords(2 downto 0);
  signal MU_HadCoreMult : DataWords(2 downto 0);
 
-- Delays
  signal DL_SeedFinder : std_logic_vector(4 downto 0);
  signal DL_UpNotDown  : std_logic;
  signal DL_Seed       : std_logic_vector(1 downto 0);
  signal DL_IsLocalMax : std_logic;
  signal DL_IsMax      : std_logic;
 
  signal DL_Overflows       : std_logic_vector(2 downto 0);
  signal DL_REtaEnvOverflow : std_logic;
  signal DL_WsCoreOverflow  : std_logic;
  signal DL_HadCoreOverflow : std_logic;
 
-- Conditions
  signal REtaCondition     : std_logic_vector(1 downto 0) := (others => '0');
  signal WsCondition       : std_logic_vector(1 downto 0) := (others => '0');
  signal HadCondition      : std_logic_vector(1 downto 0) := (others => '0');
  signal TOBEnergy         : DataWord                     := (others => '0');
  signal TOBEnergyOverflow : std_logic                    := '0';
 
  signal ConditionThr                 : DataWord;
  signal ConditionThr_d               : DataWord;
  signal EnergyThr, EnergyThr_d       : DataWord;
 
 
  --signal DMC_a       : DataWord;
  signal DMC_b0_mask : std_logic_vector(6 downto 0);
  signal DMC_b1_mask : std_logic_vector(6 downto 0);
  signal DMC_b2_mask : std_logic_vector(6 downto 0);
  signal DMC_b3_mask : std_logic_vector(6 downto 0);
 
  signal max_enable : std_logic;
  
begin
-- INPUT DATA mapping
--
-- +-------+-------+-------+
-- |   6   |   7   |   8   |
-- |       |0 1 2 3|       |
-- |       |* * * *|       |
-- +-------+-------+-------+
-- |   3   |   4   |   5   |
-- |0 1 2 3|0 1 2 3|0 1 2 3|
-- |      %|^ ^ ^ ^|%      |
-- +-------+-------+-------+
-- |       |0 1 2 3|       |
-- |       |* * * *|       |
-- |   0   |   1   |   2   |
-- +-------+-------+-------+
--
-- ^ Used in seed finder as CORE => data(4:1)
-- % Used in seed finder as ENVIRONMENT => data(0) and data (5)
-- * Used in up or down selection
 
  SF_Data(4 downto 1) <= IN_Data(4).Layer2;
  SF_Data(0)          <= IN_Data(3).Layer2(3);
  SF_Data(5)          <= IN_Data(5).Layer2(0);
 
  SF_DataUp(0)          <= IN_Data(6).Layer2(3);
  SF_DataUp(4 downto 1) <= IN_Data(7).Layer2;
  SF_DataUp(5)          <= IN_Data(8).Layer2(0);
 
  SF_DataDown(0)          <= IN_Data(0).Layer2(3);
  SF_DataDown(4 downto 1) <= IN_Data(1).Layer2;
  SF_DataDown(5)          <= IN_Data(2).Layer2(0);
 
  IM_Towers <= IN_Data;
 
-- Parameters are connected to external IPBus registers
  ParWs   <= IN_ParWs;
  ParREta <= IN_ParREta;
  ParRh   <= IN_ParHadron;
 
  EnergyThr <= IN_Energy_threshold;
  ConditionThr   <= IN_Cond_threshold;
 
  SEED_FINDER : entity work.SeedFinder  --latency 2
    port map (
      CLK            => CLK200,
      IN_Data        => SF_Data,
      IN_DataUp      => SF_DataUp,
      IN_DataDown    => SF_DataDown,
      OUT_UpNotDown  => SF_UpNotDown,
      OUT_Seed       => SF_Seed,
      OUT_IsLocalMax => SF_IsLocalMax,
      OUT_IsMax      => SF_IsMax
      );
 
  INPUT_MULTIPLEXER : entity work.egInputMultiplexer  --latency 2
    port map (
      CLK               => CLK200,
      IN_glob_Position  => IN_glob_Position,
      IN_Seed           => SF_Seed,
      IN_UpNotDown      => SF_UpNotDown,
      IN_Towers         => IM_Towers,
      OUT_EnergyL0      => IM_EnergyL0,
      OUT_EnergyL1      => IM_EnergyL1,
      OUT_EnergyL2      => IM_EnergyL2,
      OUT_EnergyL3      => IM_EnergyL3,
      OUT_REtaCoreData  => IM_REtaCoreData,
      OUT_REtaEnvData   => IM_REtaEnvData,
      OUT_WsCoreData    => IM_WsCoreData,
      OUT_WsEnvData     => IM_WsEnvData,
      OUT_HadCoreData   => IM_HadCoreData,
      OUT_HadEnvDataL1  => IM_HadEnvDataL1,
      OUT_HadEnvDataL2  => IM_HadEnvDataL2,
      OUT_HadEnvDataL03 => IM_HadEnvDataL03);
 
 
 
----------------------------------------------------------------------------------------------------------------------------------------------------------------
-- Dead Material Correction
----------------------------------------------------------------------------------------------------------------------------------------------------------------
  DEAD_MATERIAL_DELAY : entity infrastructure_lib.GeneralDelay
    generic map (
      delay => 4,
      size  => 28)
    port map (
      clk                    => CLK200,
      data_in                => (6 downto 0     => IN_ParDeadMat_b0(6 downto 0),
                                 13 downto 7    => IN_ParDeadMat_b1(6 downto 0),
                                 20 downto 14   => IN_ParDeadMat_b2(6 downto 0),
                                 27 downto 21     => IN_ParDeadMat_b3(6 downto 0)),
      data_out(6  downto  0) => DMC_b0_mask,
      data_out(13 downto 7)  => DMC_b1_mask,
      data_out(20 downto 14) => DMC_b2_mask,
      data_out(27 downto 21) => DMC_b3_mask                  
      );
 
 
  DEAD_MAT_FOR : for i in 0 to 6 generate
    Corrected_EnergyL0(i)   <= (14-i downto 0 => IM_EnergyL0(0)(15 downto i+1), others => '0') when DMC_b0_mask(i) = '1' else (others => '0');
    Corrected_EnergyL0(i+7) <= (14-i downto 0 => IM_EnergyL0(1)(15 downto i+1), others => '0') when DMC_b0_mask(i) = '1' else (others => '0');
    
    Corrected_EnergyL1(i)    <= (14-i downto 0 => IM_EnergyL1(0)(15 downto i+1), others => '0') when DMC_b1_mask(i) = '1' else (others => '0');
    Corrected_EnergyL1(i+7)  <= (14-i downto 0 => IM_EnergyL1(1)(15 downto i+1), others => '0') when DMC_b1_mask(i) = '1' else (others => '0');
    Corrected_EnergyL1(i+14) <= (14-i downto 0 => IM_EnergyL1(2)(15 downto i+1), others => '0') when DMC_b1_mask(i) = '1' else (others => '0');
    Corrected_EnergyL1(i+21) <= (14-i downto 0 => IM_EnergyL1(3)(15 downto i+1), others => '0') when DMC_b1_mask(i) = '1' else (others => '0');
    Corrected_EnergyL1(i+28) <= (14-i downto 0 => IM_EnergyL1(4)(15 downto i+1), others => '0') when DMC_b1_mask(i) = '1' else (others => '0');
    Corrected_EnergyL1(i+35) <= (14-i downto 0 => IM_EnergyL1(5)(15 downto i+1), others => '0') when DMC_b1_mask(i) = '1' else (others => '0');
            
    Corrected_EnergyL2(i)    <= (14-i downto 0 => IM_EnergyL2(0)(15 downto i+1), others => '0') when DMC_b2_mask(i) = '1' else (others => '0');
    Corrected_EnergyL2(i+7)  <= (14-i downto 0 => IM_EnergyL2(1)(15 downto i+1), others => '0') when DMC_b2_mask(i) = '1' else (others => '0');
    Corrected_EnergyL2(i+14) <= (14-i downto 0 => IM_EnergyL2(2)(15 downto i+1), others => '0') when DMC_b2_mask(i) = '1' else (others => '0');
    Corrected_EnergyL2(i+21) <= (14-i downto 0 => IM_EnergyL2(3)(15 downto i+1), others => '0') when DMC_b2_mask(i) = '1' else (others => '0');
    Corrected_EnergyL2(i+28) <= (14-i downto 0 => IM_EnergyL2(4)(15 downto i+1), others => '0') when DMC_b2_mask(i) = '1' else (others => '0');
    Corrected_EnergyL2(i+35) <= (14-i downto 0 => IM_EnergyL2(5)(15 downto i+1), others => '0') when DMC_b2_mask(i) = '1' else (others => '0');
 
    Corrected_EnergyL3(i)   <= (14-i downto 0 => IM_EnergyL3(0)(15 downto i+1), others => '0') when DMC_b3_mask(i) = '1' else (others => '0');
    Corrected_EnergyL3(i+7) <= (14-i downto 0 => IM_EnergyL3(1)(15 downto i+1), others => '0') when DMC_b3_mask(i) = '1' else (others => '0');
 
  end generate DEAD_MAT_FOR;
 
 
-------------------------------------------------------------------------------
-- ADDERS
-------------------------------------------------------------------------------
 
-- Energy
  MULTI_ADDER_ENERGY : entity work.MultiAdder
    generic map (
      stage => 7,
      delay => 0)
    port map (
      CLK          => CLK200,
      IN_Words     => IM_EnergyL0 & IM_EnergyL1&IM_EnergyL2&IM_EnergyL3 & Corrected_EnergyL0 &     
                      Corrected_EnergyL1 & Corrected_EnergyL2 & Corrected_EnergyL3,  --128
      OUT_Overflow => MA_EnergyOverflow,
      OUT_Word     => MA_EnergySum);
 
-- REta
  MULTI_ADDER_RETA_ENV : entity work.MultiAdder
    generic map (
      stage => 4,
      delay => 0)
    port map (
      CLK          => CLK200,
      IN_Words     => IM_REtaEnvData & ZERO_DATA_WORD  ,  -- 15+1
      OUT_Overflow => MA_REtaEnvOverflow,
      OUT_Word     => MA_REtaEnvSum);
 
  MULTI_ADDER_RETA_CORE : entity work.MultiAdder
    generic map (
      stage => 3,
      delay => 4)
    port map (
      CLK          => CLK200,
      IN_Words     => IM_REtaCoreData & ZERO_DATA_WORD&ZERO_DATA_WORD  ,  -- 6+2
      OUT_Overflow => MA_REtaCoreOverflow,
      OUT_Word     => MA_REtaCoreSum);
 
--Ws
  MULTI_ADDER_WS_CORE : entity work.MultiAdder
    generic map (
      stage => 4,
      delay => 0)
    port map (
      CLK          => CLK200,
      IN_Words     => IM_WsCoreData&ZERO_DATA_WORD&ZERO_DATA_WORD&ZERO_DATA_WORD&ZERO_DATA_WORD,  --12+4
      OUT_Overflow => MA_WsCoreOverflow,
      OUT_Word     => MA_WsCoreSum);
 
  MULTI_ADDER_WS_ENV : entity work.MultiAdder
    generic map (
      stage => 4,
      delay => 3)
    port map (
      CLK          => CLK200,
      IN_Words     => IM_WsEnvData &ZERO_DATA_WORD ,  --15+1
      OUT_Overflow => MA_WsEnvOverflow,
      OUT_Word     => MA_WsEnvSum);
 
--Hadron
  MULTI_ADDER_HAD_CORE : entity work.MultiAdder
    generic map (
      stage => 4,
      delay => 0)
    port map (
      CLK          => CLK200,
      IN_Words     => IM_HadCoreData(13 downto 0)&ZERO_DATA_WORD&ZERO_DATA_WORD,  
      OUT_Overflow => MA_HadCoreOverflow,
      OUT_Word     => MA_HadCoreSum);
 
  MULTI_ADDER_HAD_ENV : entity work.MultiAdder
    generic map (
      stage => 4,
      delay => 3)
    port map (
      CLK          => CLK200,
      IN_Words     => IM_HadEnvDataL1&IM_HadEnvDataL2&IM_HadEnvDataL03&ZERO_DATA_WORD&ZERO_DATA_WORD,  --14+2
      OUT_Overflow => MA_HadEnvOverflow,
      OUT_Word     => MA_HadEnvSum);
 
 
-------------------------------------------------------------------------------
-- MULTIPLIERS
-------------------------------------------------------------------------------
 
-- REta
  RETA_MULTIPLIER : entity work.MultiMultiplier  --delay 3
    generic map (parameters => 3)
    port map (
      CLK           => CLK200,
      IN_Word       => MA_REtaEnvSum,
      IN_parameters => ParREta,
      OUT_Overflow  => MU_REtaEnvOverflows,
      OUT_Words     => MU_REtaEnvMult
      );
 
-- Ws
  WS_MULTIPLIER : entity work.MultiMultiplier  --delay 3
    generic map (parameters => 3)
    port map (
      CLK           => CLK200,
      IN_Word       => MA_WsCoreSum,
      IN_parameters => ParWs,
      OUT_Overflow  => MU_WsCoreOverflows,
      OUT_Words     => MU_WsCoreMult
      );
 
--hadronic
  HADRON_MULTIPLIER : entity work.MultiMultiplier  --delay 3
    port map (
      CLK           => CLK200,
      IN_Word       => MA_HadCoreSum,
      IN_parameters => ParRh,
      OUT_Overflow  => MU_HadCoreOverflows,
      OUT_Words     => MU_HadCoreMult
      );
 
  Condition_threshold_delay : entity work.Delay
    generic map (
      delay => 4)
    port map (
      CLK      => CLK200,
      IN_Word  => ConditionThr,
      OUT_Word => ConditionThr_d);
 
  Energy_threshold_delay : entity work.Delay
    generic map (
      delay => 3)
    port map (
      CLK      => CLK200,
      IN_Word  => EnergyThr,
      OUT_Word => EnergyThr_d);
 
-------------------------------------------------------------------------------
-- SEED AND OVERFLOWS DELAY
-------------------------------------------------------------------------------
 
  SEED_DELAY : entity infrastructure_lib.GeneralDelay
    generic map (
      delay => 9,
      size  => 5)
    port map (
      clk      => CLK200,
      data_in  => (0 => SF_IsMax, 1 => SF_IsLocalMax, 2 => SF_UpNotDown, 4 downto 3   => SF_Seed),
      data_out => DL_SeedFinder
      );
 
 
  DL_IsMax      <= DL_SeedFinder(0);
  DL_IsLocalMax <= DL_SeedFinder(1);
  DL_UpNotDown  <= DL_SeedFinder(2);
  DL_Seed       <= DL_SeedFinder(4 downto 3);
 
  OVERFLOW_DELAY : entity infrastructure_lib.GeneralDelay
    generic map (
      delay => 2,
      size  => 3)
    port map (
      clk      => CLK200,
      data_in  => (0 => MA_REtaEnvOverflow, 1 => MA_WsCoreOverflow, 2 => MA_HadCoreOverflow),
      data_out => DL_Overflows
      );
 
  DL_REtaEnvOverflow <= DL_Overflows(0);
  DL_WsCoreOverflow  <= DL_Overflows(1);
  DL_HadCoreOverflow <= DL_Overflows(2);
 
-----------------------------------------------------------------------------
-- TRIGGER-OBJECT CONDITIONS
-----------------------------------------------------------------------------
  CONDITIONS : process (CLK200)
    variable RetaShifted, WsShifted, HadShifted : DataWord;
  begin
    if rising_edge(CLK200) then
      -- add energhy threshold here
      if MA_EnergyOverflow = '1' then
        TOBEnergy         <= (others => '1');
        TOBEnergyOverflow <= MA_EnergyOverflow;
        max_enable        <= '1';        
      elsif MA_EnergySum < EnergyThr_d then
        TOBEnergy         <= (others => '0');
        TOBEnergyOverflow <= '0';
        max_enable        <= '0';
      else
        TOBEnergy         <= MA_EnergySum;
        TOBEnergyOverflow <= MA_EnergyOverflow;
        max_enable        <= '1';        
      end if;
 
 
      -- REta condition
      RetaShifted := BitLeftShift(MA_REtaCoreSum, 3);
 
      REtaCondition <= EvaluateCondition (
        Pass_overflow        => MA_REtaCoreOverflow,
        Fail_overflow        => DL_REtaEnvOverflow,
        E_threshold          => ConditionThr_d,
        Total_Energy         => MA_EnergySum,
        Total_Energy_of      => MA_EnergyOverflow,
        Condition_Energy     => RetaShifted,
        Thresholds           => MU_REtaEnvMult,
        Thresholds_overflows => MU_REtaEnvOverflows);
 
      -- Ws condition
      WsShifted := BitLeftShift(MA_WsEnvSum, 5);
      WsCondition <= EvaluateCondition (
        Pass_overflow        => MA_WsEnvOverflow,
        Fail_overflow        => DL_WsCoreOverflow,
        E_threshold          => ConditionThr_d,
        Total_Energy_of      => MA_EnergyOverflow,
        Total_Energy         => MA_EnergySum,
        Condition_Energy     => WsShifted,
        Thresholds           => MU_WsCoreMult,
        Thresholds_overflows => MU_WsCoreOverflows);
 
      -- hadronic conditions
      HadShifted := BitLeftShift(MA_HadEnvSum, 3);
      HadCondition <= EvaluateCondition (
        Pass_overflow        => MA_HadEnvOverflow,
        Fail_overflow        => DL_HadCoreOverflow,
        E_threshold          => ConditionThr_d,
        Total_Energy_of      => MA_EnergyOverflow,
        Total_Energy         => MA_EnergySum,
        Condition_Energy     => HadShifted,
        Thresholds           => MU_HadCoreMult,
        Thresholds_overflows => MU_HadCoreOverflows);
 
    end if;
  end process;
 
-- TOB building
  OUT_TOB.Core.Version   <= EG_ALGO_VERSION; 
  OUT_TOB.Core.Energy    <= to_TOBEnergy(TOBEnergy);
  OUT_TOB.Core.EnergyOF  <= TOBEnergyOverflow;
  OUT_TOB.Core.REta      <= REtaCondition;
  OUT_TOB.Core.ws        <= WsCondition;
  OUT_TOB.Core.Had       <= HadCondition;
  OUT_TOB.Core.UpNotDown <= DL_UpNotDown;
  OUT_TOB.Core.Seed      <= DL_Seed;
  OUT_TOB.Core.Max       <= DL_IsMax;
  OUT_TOB.Core.LocalMax  <= DL_IsLocalMax and max_enable;
  OUT_TOB.Position.Eta   <= (others => '0');
  OUT_TOB.Position.Phi   <= (others => '0');
 
end Behavioral;