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eFEX firmware
1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards
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Core of the BDT tau Algorithm. More...
Go to the source code of this file.
Entities | |
| AlgoCore_tau_bdt | entity |
| Core of the electromagnetic algorithm. More... | |
| Behavioral | architecture |
| Core of the electromagnetic algorithm. More... | |
Core of the BDT tau Algorithm.
The total latency of this block is 10 clock cycles. Inputs: IN_ParBDT: array of 3 8-bit BDT thresholds used to compute the BDT condition, allowing loose/medium/tight working points. These values are compared with the 8 MSB bits of the BDT score to produce a number between 0 and 3 which is written to OUT_TOB.Core.BDT IN_ParFrac: array of 3 8-bit parameters used to multiply the EM estimate, compare the resulting 3 values to the HAD estimate and produce a loose/medium/tight condition for triggering on LLPs which is written out to OUT_TOB.Core.Frac IN_Min_E_threshold: A 16-bit ET threshold used to compute OUT_TOB.Core.Energy. If the energy is below this threshold, The latter field will be all zeros. IN_Min_BDT_E_threshold: A 16-bit ET threshold for low ET cutoff of the BDT condition. Below it the BDT WP is set to "tight". IN_Max_cond_E_threshold: A 16-bit ET threshold for high ET cutoff of both BDT and hadronic fraction conditions. Beyond it the corresponding WP is set to "tight". IN_Data: an array of TriggerTowers with nine elements, representing a single TOB.
The input data is mapped like this: +----—+----—+----—+ | 6 | 7 | 8 | | |0 1 2 3| | | | | | +----—+----—+----—+ | 3 | 4 | 5 | | | |0 1 2 3| | | | | +----—+----—+----—+
| 0 1 2 3 | ||
|---|---|---|
| 0 | 1 | 2 |
+----—+----—+----—+
The BDT's inputs are sums over groups of symmetrically positioned supercells around the TOB axis. For example, a sum over all the corner supercells of layer 2 is one variable. The BDT has 11 such variables. The design is constructed of several stages:
Definition in file AlgoCore_tau_bdt.vhd.
1.9.1