eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

Back to eFEX documentation
Components | Instantiations | Signals
Behavioral Architecture Reference

Core of the electromagnetic algorithm. More...

Components

Mult 

Signals

TOBEnergy  DataWord
C_IN_TOBEnergy  DataWord
C_IN_FracTOBEnergy  DataWord
TOBEnergyOverflow  std_logic
C_IN_TOBEnergyOverflow  std_logic
C_IN_FracTOBEnergyOverflow  std_logic
C_IN_EnergyThr  DataWord
C_IN_BDTMaxEnergyThr  DataWord
C_IN_BDTMinEnergyThr  DataWord
C_IN_BDTTOBEnergy  DataWord
C_IN_BDTTOBEnergyOverflow  std_logic
SF_IsMax  std_logic
C_IN_IsMax  std_logic
C_OUT_IsMax  std_logic
Final_IsMax  std_logic := ' 0 '
Final_TOBEnergy  DataWord := ( others = > ' 0 ' )
Final_TOBEnergyOverflow  std_logic := ' 0 '
C_OUT_TOBEnergy  DataWord
C_OUT_TOBEnergyOverflow  std_logic
BDTScore  std_logic_vector ( BDT_SCORE_WIDTH- 1 downto 0 )
C_IN_BDTScore  std_logic_vector ( BDT_SCORE_WIDTH- 1 downto 0 )
BDTThresholds  AlgoParameters ( 2 downto 0 )
C_IN_BDTThr  AlgoParameters ( 2 downto 0 )
Final_BDTCondition  std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
C_OUT_BDTCondition  std_logic_vector ( 1 downto 0 )
Final_BDTScore  std_logic_vector ( BDT_SCORE_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
C_OUT_BDTScore  std_logic_vector ( BDT_SCORE_WIDTH- 1 downto 0 )
FracEnvSumOverflow  std_logic
C_IN_FracEnvSumOverflow  std_logic
FracCoreSumOverflow  std_logic
C_IN_FracCoreSumOverflow  std_logic
FracCoreSum  DataWord
C_IN_FracCoreSum  DataWord
FracEnvMultOverflows  std_logic_vector ( 2 downto 0 )
C_IN_FracEnvMultOverflows  std_logic_vector ( 2 downto 0 )
FracEnvMult  DataWords ( 2 downto 0 )
C_IN_FracEnvMult  DataWords ( 2 downto 0 )
C_IN_Frac_ET_Thr  DataWord
Final_FracCondition  std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
C_OUT_FracCondition  std_logic_vector ( 1 downto 0 )
ParFrac  AlgoParameters ( 2 downto 0 )
M_IN_ParFrac  AlgoParameters ( 2 downto 0 )
output_data  DataWords ( BDT_N_VARIABLES+ 10 downto 0 )
output_of_data  std_logic_vector ( BDT_N_VARIABLES+ 10 downto 0 )
BDTScore_vld  std_logic
SF_sum  DataWords ( 8 downto 0 )
SF_of  std_logic_vector ( 8 downto 0 )
BDTVars_val  DataWords ( BDT_N_VARIABLES- 1 downto 0 )
FracEnvSum  DataWord
M_IN_FracEnvSum  DataWord
DelayTree_out  DataWords ( 33 downto 0 )
DelayTree_in  DataWords ( 28 downto 0 )

Instantiations

adder_tree  AdderTree <Entity AdderTree>
tau_seed_finder  TauSeedFinder <Entity TauSeedFinder>
bdt  BDTModel <Entity BDTModel>
delay_tree  DelayTree <Entity DelayTree>
frac_multiplier  MultiMultiplier <Entity MultiMultiplier>
conditions_energy_and_seed  TauConditionsEnergyAndSeed <Entity TauConditionsEnergyAndSeed>
conditions_bdt  TauConditionsBDT <Entity TauConditionsBDT>
conditions_frac  TauConditionsFrac <Entity TauConditionsFrac>

Detailed Description

Core of the electromagnetic algorithm.

The total latency of this block is 10 clock cycles, this is a table representing the timing:

clock cycle 0 1 2 3 4 5 6 7 8 9 10
RAM address 0 1 2 3 4 0 1 2 3 4 0
seed finder X X
In mux X X
Adders env X X X X
Addders core X X X X X X X
Multipliers X X X
Seed delay X X X X X X X X X
TOB energy X X
Threshold delay X X X
Conditions X X
Dead Mat. Corr. X
DMC delay X X

At clock cycle 0 the data is provided to the algorithm.

At clock cycle 1, the seed is ready and so is the data coming out of the input multiplexer, which is provided to the adders.

At clock cycle 5, the envoronment sums are ready and fed into the multipliers.

At clock cycle 8, all the sums and the multiplications are done and the valued are fed into the conditions

At clock cycle 8 also the energy threshold is applied.

At clock cycle 10 the TOBs are formed with the conditions bits and the Energy

The parameters used to evaluate the conditions are read from the RAM at clock cycle 0 or 5 (the RAM address goes form 0 to 4).

A delay of 2 clock cycles is used to pipeline the correct value for Dead Materal Correction (DMC) parameters that are read at clock cycle 2, i.e. when data is provided to the adders.

A delay of 3 clock cycles is used to delay the energy thresholds which are read at clock cycle 8, i.e. when the conditions are evaluated.

Author
Francesco Gonnella

Definition at line 76 of file AlgoCore_tau_bdt.vhd.


The documentation for this class was generated from the following file: