eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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aurora_wrapper_hub2.vhd
1 
2  library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use IEEE.NUMERIC_STD.ALL;
5 
6  entity aurora_wrapper_hub2 is
7 
8  Port (
9  -- TX Stream Interface
10  s_axi_tx_tdata : in std_logic_vector(63 downto 0);
11  s_axi_tx_tvalid : in std_logic;
12  s_axi_tx_tready : out std_logic;
13  s_axi_tx_tkeep : in std_logic_vector(7 downto 0);
14  s_axi_tx_tlast : in std_logic;
15  -- User Flow Control TX Interface
16  s_axi_ufc_tx_req : in std_logic;
17  s_axi_ufc_tx_ms : in std_logic_vector(2 downto 0);
18  s_axi_ufc_tx_ack : out std_logic;
19  -- V7 Serial I/O
20  txp : out std_logic_vector(0 to 3);
21  txn : out std_logic_vector(0 to 3);
22  -- GT Reference Clock Interface
23 
24  gt_refclk1_p : in std_logic;
25  gt_refclk1_n : in std_logic;
26  -- gt control
27  aurora_gt0_txctrl :in std_logic_vector( 23 downto 0);
28  aurora_gt1_txctrl :in std_logic_vector( 23 downto 0);
29  aurora_gt2_txctrl :in std_logic_vector( 23 downto 0);
30  aurora_gt3_txctrl :in std_logic_vector( 23 downto 0);
31  -- Error Detection Interface
32  tx_hard_err : out std_logic;
33  -- Status
34  tx_channel_up : out std_logic;
35  tx_lane_up : out std_logic_vector(0 to 3);
36  -- System Interface
37  user_clk_out : out std_logic;
38  sys_reset_out : out std_logic;
39  gt_reset : in std_logic;
40  tx_system_reset : in std_logic;
41  tx_lock : out std_logic;
42  init_clk : in std_logic;
43  init_clk_out : out std_logic;
44  pll_not_locked : out std_logic;
45  tx_resetdone : out std_logic
46 
47 );
48 end aurora_wrapper_hub2;
49 
50 architecture Behavioral of aurora_wrapper_hub2 is
51 
52 
53  component efex_aurora_hub2_support
54  port (
55  -- TX Stream Interface
56  s_axi_tx_tdata : in std_logic_vector(63 downto 0);
57  s_axi_tx_tvalid : in std_logic;
58  s_axi_tx_tready : out std_logic;
59  s_axi_tx_tkeep : in std_logic_vector(7 downto 0);
60  s_axi_tx_tlast : in std_logic;
61 
62  -- User Flow Control TX Interface
63  s_axi_ufc_tx_req : in std_logic;
64  s_axi_ufc_tx_ms : in std_logic_vector(2 downto 0);
65  s_axi_ufc_tx_ack : out std_logic;
66 
67  -- V5 Serial I/O
68  txp : out std_logic_vector(0 to 3);
69  txn : out std_logic_vector(0 to 3);
70  -- GT Reference Clock Interface
71  gt_refclk1_p : in std_logic;
72  gt_refclk1_n : in std_logic;
73  -- Error Detection Interface
74  tx_hard_err : out std_logic;
75  -- Status
76  tx_channel_up : out std_logic;
77  tx_lane_up : out std_logic_vector(0 to 3);
78  -- System Interface
79  user_clk_out : out std_logic;
80  sys_reset_out : out std_logic;
81  gt_reset : in std_logic;
82  tx_system_reset : in std_logic;
83  tx_lock : out std_logic;
84  init_clk : in std_logic;
85  init_clk_out : out std_logic;
86  pll_not_locked_out : out std_logic;
87  tx_resetdone_out : out std_logic;
88 
89  gt0_cplllock_out : out std_logic;
90  gt0_txresetdone_out : out std_logic;
91  gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
92  ------------------------ TX Configurable Driver Ports ----------------------
93  gt0_txpostcursor_in : in std_logic_vector(4 downto 0);
94  gt0_txprecursor_in : in std_logic_vector(4 downto 0);
95  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
96  gt0_txchardispmode_in : in std_logic_vector(1 downto 0);
97  gt0_txchardispval_in : in std_logic_vector(1 downto 0);
98  gt0_txdiffctrl_in : in std_logic_vector(3 downto 0);
99  gt0_txmaincursor_in : in std_logic_vector(6 downto 0);
100  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
101  gt0_txpolarity_in : in std_logic;
102  gt0_tx_buf_err_out : out std_logic;
103  ------------------ Transmit Ports - Pattern Generator Ports ----------------
104  gt0_txprbsforceerr_in : in std_logic;
105  gt0_txprbssel_in : in std_logic_vector(2 downto 0);
106  ------------------- Transmit Ports - TX Data Path interface -----------------
107  gt0_txpcsreset_in : in std_logic;
108  gt0_txinhibit_in : in std_logic;
109  gt0_txpmareset_in : in std_logic;
110 
111  gt1_cplllock_out : out std_logic;
112  gt1_txresetdone_out : out std_logic;
113  gt1_txbufstatus_out : out std_logic_vector(1 downto 0);
114  ------------------------ TX Configurable Driver Ports ----------------------
115  gt1_txpostcursor_in : in std_logic_vector(4 downto 0);
116  gt1_txprecursor_in : in std_logic_vector(4 downto 0);
117  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
118  gt1_txchardispmode_in : in std_logic_vector(1 downto 0);
119  gt1_txchardispval_in : in std_logic_vector(1 downto 0);
120  gt1_txdiffctrl_in : in std_logic_vector(3 downto 0);
121  gt1_txmaincursor_in : in std_logic_vector(6 downto 0);
122  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
123  gt1_txpolarity_in : in std_logic;
124  gt1_tx_buf_err_out : out std_logic;
125  ------------------ Transmit Ports - Pattern Generator Ports ----------------
126  gt1_txprbsforceerr_in : in std_logic;
127  gt1_txprbssel_in : in std_logic_vector(2 downto 0);
128  ------------------- Transmit Ports - TX Data Path interface -----------------
129  gt1_txpcsreset_in : in std_logic;
130  gt1_txinhibit_in : in std_logic;
131  gt1_txpmareset_in : in std_logic;
132 
133  gt2_cplllock_out : out std_logic;
134  gt2_txresetdone_out : out std_logic;
135  gt2_txbufstatus_out : out std_logic_vector(1 downto 0);
136  ------------------------ TX Configurable Driver Ports ----------------------
137  gt2_txpostcursor_in : in std_logic_vector(4 downto 0);
138  gt2_txprecursor_in : in std_logic_vector(4 downto 0);
139  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
140  gt2_txchardispmode_in : in std_logic_vector(1 downto 0);
141  gt2_txchardispval_in : in std_logic_vector(1 downto 0);
142  gt2_txdiffctrl_in : in std_logic_vector(3 downto 0);
143  gt2_txmaincursor_in : in std_logic_vector(6 downto 0);
144  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
145  gt2_txpolarity_in : in std_logic;
146  gt2_tx_buf_err_out : out std_logic;
147  ------------------ Transmit Ports - Pattern Generator Ports ----------------
148  gt2_txprbsforceerr_in : in std_logic;
149  gt2_txprbssel_in : in std_logic_vector(2 downto 0);
150  ------------------- Transmit Ports - TX Data Path interface -----------------
151  gt2_txpcsreset_in : in std_logic;
152  gt2_txinhibit_in : in std_logic;
153  gt2_txpmareset_in : in std_logic;
154 
155  gt3_cplllock_out : out std_logic;
156  gt3_txresetdone_out : out std_logic;
157  gt3_txbufstatus_out : out std_logic_vector(1 downto 0);
158  ------------------------ TX Configurable Driver Ports ----------------------
159  gt3_txpostcursor_in : in std_logic_vector(4 downto 0);
160  gt3_txprecursor_in : in std_logic_vector(4 downto 0);
161  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
162  gt3_txchardispmode_in : in std_logic_vector(1 downto 0);
163  gt3_txchardispval_in : in std_logic_vector(1 downto 0);
164  gt3_txdiffctrl_in : in std_logic_vector(3 downto 0);
165  gt3_txmaincursor_in : in std_logic_vector(6 downto 0);
166  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
167  gt3_txpolarity_in : in std_logic;
168  gt3_tx_buf_err_out : out std_logic;
169  ------------------ Transmit Ports - Pattern Generator Ports ----------------
170  gt3_txprbsforceerr_in : in std_logic;
171  gt3_txprbssel_in : in std_logic_vector(2 downto 0);
172  ------------------- Transmit Ports - TX Data Path interface -----------------
173  gt3_txpcsreset_in : in std_logic;
174  gt3_txinhibit_in : in std_logic;
175  gt3_txpmareset_in : in std_logic;
176 
177 drpclk_in : in std_logic;
178 drpaddr_in : in std_logic_vector(8 downto 0);
179 drpdi_in : in std_logic_vector(15 downto 0);
180 drpdo_out : out std_logic_vector(15 downto 0);
181 drpen_in : in std_logic;
182 drprdy_out : out std_logic;
183 drpwe_in : in std_logic;
184 drpaddr_in_lane1 : in std_logic_vector(8 downto 0);
185 drpdi_in_lane1 : in std_logic_vector(15 downto 0);
186 drpdo_out_lane1 : out std_logic_vector(15 downto 0);
187 drpen_in_lane1 : in std_logic;
188 drprdy_out_lane1 : out std_logic;
189 drpwe_in_lane1 : in std_logic;
190 drpaddr_in_lane2 : in std_logic_vector(8 downto 0);
191 drpdi_in_lane2 : in std_logic_vector(15 downto 0);
192 drpdo_out_lane2 : out std_logic_vector(15 downto 0);
193 drpen_in_lane2 : in std_logic;
194 drprdy_out_lane2 : out std_logic;
195 drpwe_in_lane2 : in std_logic;
196 drpaddr_in_lane3 : in std_logic_vector(8 downto 0);
197 drpdi_in_lane3 : in std_logic_vector(15 downto 0);
198 drpdo_out_lane3 : out std_logic_vector(15 downto 0);
199 drpen_in_lane3 : in std_logic;
200 drprdy_out_lane3 : out std_logic;
201 drpwe_in_lane3 : in std_logic;
202 
203 
204  power_down : in std_logic;
205  loopback : in std_logic_vector(2 downto 0)
206  );
207 end component;
208 
209 signal drpclk_i : std_logic;
210 signal daddr_in_i : std_logic_vector(8 downto 0);
211 signal dclk_in_i : std_logic;
212 signal den_in_i : std_logic;
213 signal di_in_i : std_logic_vector(15 downto 0);
214 signal drdy_out_unused_i : std_logic;
215 signal drpdo_out_unused_i : std_logic_vector(15 downto 0);
216 signal dwe_in_i : std_logic;
217 signal daddr_in_LANE1_i : std_logic_vector(8 downto 0);
218 signal dclk_in_LANE1_i : std_logic;
219 signal den_in_LANE1_i : std_logic;
220 signal di_in_LANE1_i : std_logic_vector(15 downto 0);
221 signal drdy_out_LANE1_unused_i : std_logic;
222 signal drpdo_out_LANE1_unused_i : std_logic_vector(15 downto 0);
223 signal dwe_in_LANE1_i : std_logic;
224 signal daddr_in_LANE2_i : std_logic_vector(8 downto 0);
225 signal dclk_in_LANE2_i : std_logic;
226 signal den_in_LANE2_i : std_logic;
227 signal di_in_LANE2_i : std_logic_vector(15 downto 0);
228 signal drdy_out_LANE2_unused_i : std_logic;
229 signal drpdo_out_LANE2_unused_i : std_logic_vector(15 downto 0);
230 signal dwe_in_LANE2_i : std_logic;
231 signal daddr_in_LANE3_i : std_logic_vector(8 downto 0);
232 signal dclk_in_LANE3_i : std_logic;
233 signal den_in_LANE3_i : std_logic;
234 signal di_in_LANE3_i : std_logic_vector(15 downto 0);
235 signal drdy_out_LANE3_unused_i : std_logic;
236 signal drpdo_out_LANE3_unused_i : std_logic_vector(15 downto 0);
237 signal dwe_in_LANE3_i : std_logic;
238 signal power_down_i : std_logic;
239 signal loopback_i : std_logic_vector(2 downto 0);
240 
241 signal tied_to_ground_i : std_logic;
242 signal tied_to_ground_vec_lanes : std_logic_vector(0 to 3);
243 signal tied_to_gnd_vec_i : std_logic_vector(0 to 63);
244  -- TX AXI PDU I/F wires
245 
246 
247 
248 
249 begin
250 
251  -- System Interface
252  power_down_i <= '0';
253  loopback_i <= "000";
254  daddr_in_i <= (others=>'0');
255  dclk_in_i <= '0';
256  den_in_i <= '0';
257  di_in_i <= (others=>'0');
258  dwe_in_i <= '0';
259  daddr_in_LANE1_i <= (others=>'0');
260  dclk_in_LANE1_i <= '0';
261  den_in_LANE1_i <= '0';
262  di_in_LANE1_i <= (others=>'0');
263  dwe_in_LANE1_i <= '0';
264  daddr_in_LANE2_i <= (others=>'0');
265  dclk_in_LANE2_i <= '0';
266  den_in_LANE2_i <= '0';
267  di_in_LANE2_i <= (others=>'0');
268  dwe_in_LANE2_i <= '0';
269  daddr_in_LANE3_i <= (others=>'0');
270  dclk_in_LANE3_i <= '0';
271  den_in_LANE3_i <= '0';
272  di_in_LANE3_i <= (others=>'0');
273  dwe_in_LANE3_i <= '0';
274 
275 
276 
277  aurora_module_i : efex_aurora_hub2_support
278  port map (
279  -- AXI TX Interface
280  s_axi_tx_tdata => s_axi_tx_tdata ,
281  s_axi_tx_tkeep => s_axi_tx_tkeep ,
282  s_axi_tx_tvalid => s_axi_tx_tvalid,
283  s_axi_tx_tlast => s_axi_tx_tlast ,
284  s_axi_tx_tready => s_axi_tx_tready,
285  -- User Flow Control TX Interface
286  s_axi_ufc_tx_req => s_axi_ufc_tx_req,
287  s_axi_ufc_tx_ms => s_axi_ufc_tx_ms,
288  s_axi_ufc_tx_ack => s_axi_ufc_tx_ack,
289  -- Serial IO
290  txn => txn,
291  txp => txp,
292  gt_refclk1_p => gt_refclk1_p,
293  gt_refclk1_n => gt_refclk1_n,
294 
295  -- Error Detection Interface
296  tx_hard_err => tx_hard_err,
297  -- Status
298  tx_channel_up => tx_channel_up,
299  tx_lane_up => tx_lane_up,
300  -- System Interface
301  user_clk_out => user_clk_out,
302  sys_reset_out => sys_reset_out,
303  tx_system_reset => tx_system_reset,
304  power_down => power_down_i,
305  gt_reset => gt_reset,
306  tx_lock => tx_lock,
307  init_clk => init_clk,
308  init_clk_out => init_clk_out,
309  pll_not_locked_out => pll_not_locked,
310  tx_resetdone_out => tx_resetdone,
311 
312 
313  gt0_cplllock_out => open,
314 ---------------------- gt0 debug ports start ---------------------------
315  gt0_txresetdone_out => open,
316  gt0_txbufstatus_out => open,
317  ------------------------ TX Configurable Driver Ports ----------------------
318  gt0_txpostcursor_in => aurora_gt0_txctrl(12 downto 8),
319  gt0_txprecursor_in => aurora_gt0_txctrl(20 downto 16),
320  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
321  gt0_txchardispmode_in => "00",
322  gt0_txchardispval_in => "00",
323  gt0_txdiffctrl_in => aurora_gt0_txctrl(3 downto 0),
324  gt0_txmaincursor_in => "0000000",
325  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
326  gt0_txpolarity_in => tied_to_ground_i,
327  gt0_tx_buf_err_out => OPEN,
328  ------------------ Transmit Ports - Pattern Generator Ports ----------------
329  gt0_txprbsforceerr_in => tied_to_ground_i,
330  gt0_txprbssel_in => "000",
331  ------------------- Transmit Ports - TX Data Path interface -----------------
332  gt0_txpcsreset_in => tied_to_ground_i,
333  gt0_txinhibit_in => tied_to_ground_i,
334  gt0_txpmareset_in => tied_to_ground_i,
335 
336 ---------------------- gt0 debug ports end ---------------------------
337 
338  gt1_cplllock_out => open,
339 ---------------------- gt1 debug ports start ---------------------------
340  gt1_txresetdone_out => open,
341  gt1_txbufstatus_out => open,
342  ------------------------ TX Configurable Driver Ports ----------------------
343  gt1_txpostcursor_in => aurora_gt1_txctrl(12 downto 8),
344  gt1_txprecursor_in => aurora_gt1_txctrl(20 downto 16),
345  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
346  gt1_txchardispmode_in => "00",
347  gt1_txchardispval_in => "00",
348  gt1_txdiffctrl_in => aurora_gt1_txctrl(3 downto 0),
349  gt1_txmaincursor_in => "0000000",
350  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
351  gt1_txpolarity_in => tied_to_ground_i,
352  gt1_tx_buf_err_out => OPEN,
353  ------------------ Transmit Ports - Pattern Generator Ports ----------------
354  gt1_txprbsforceerr_in => tied_to_ground_i,
355  gt1_txprbssel_in => "000",
356  ------------------- Transmit Ports - TX Data Path interface -----------------
357  gt1_txpcsreset_in => tied_to_ground_i,
358  gt1_txinhibit_in => tied_to_ground_i,
359  gt1_txpmareset_in => tied_to_ground_i,
360 
361 ---------------------- gt1 debug ports end ---------------------------
362 
363  gt2_cplllock_out => open,
364 ---------------------- gt2 debug ports start ---------------------------
365  gt2_txresetdone_out => open,
366  gt2_txbufstatus_out => open,
367  ------------------------ TX Configurable Driver Ports ----------------------
368  gt2_txpostcursor_in => aurora_gt2_txctrl(12 downto 8),
369  gt2_txprecursor_in => aurora_gt2_txctrl(20 downto 16),
370  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
371  gt2_txchardispmode_in => "00",
372  gt2_txchardispval_in => "00",
373  gt2_txdiffctrl_in => aurora_gt2_txctrl(3 downto 0),
374  gt2_txmaincursor_in => "0000000",
375  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
376  gt2_txpolarity_in => tied_to_ground_i,
377  gt2_tx_buf_err_out => OPEN,
378  ------------------ Transmit Ports - Pattern Generator Ports ----------------
379  gt2_txprbsforceerr_in => tied_to_ground_i,
380  gt2_txprbssel_in => "000",
381  ------------------- Transmit Ports - TX Data Path interface -----------------
382  gt2_txpcsreset_in => tied_to_ground_i,
383  gt2_txinhibit_in => tied_to_ground_i,
384  gt2_txpmareset_in => tied_to_ground_i,
385 
386 ---------------------- gt2 debug ports end ---------------------------
387 
388  gt3_cplllock_out => open,
389 ---------------------- gt3 debug ports start ---------------------------
390  gt3_txresetdone_out => open,
391  gt3_txbufstatus_out => open,
392  ------------------------ TX Configurable Driver Ports ----------------------
393  gt3_txpostcursor_in => aurora_gt3_txctrl(12 downto 8),
394  gt3_txprecursor_in => aurora_gt3_txctrl(20 downto 16),
395  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
396  gt3_txchardispmode_in => "00",
397  gt3_txchardispval_in => "00",
398  gt3_txdiffctrl_in => aurora_gt3_txctrl(3 downto 0),
399  gt3_txmaincursor_in => "0000000",
400  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
401  gt3_txpolarity_in => tied_to_ground_i,
402  gt3_tx_buf_err_out => OPEN,
403  ------------------ Transmit Ports - Pattern Generator Ports ----------------
404  gt3_txprbsforceerr_in => tied_to_ground_i,
405  gt3_txprbssel_in => "000",
406  ------------------- Transmit Ports - TX Data Path interface -----------------
407  gt3_txpcsreset_in => tied_to_ground_i,
408  gt3_txinhibit_in => tied_to_ground_i,
409  gt3_txpmareset_in => tied_to_ground_i,
410 
411 ---------------------- gt3 debug ports end ---------------------------
412 
413 drpclk_in => drpclk_i,
414 drpaddr_in => daddr_in_i,
415 drpen_in => den_in_i,
416 drpdi_in => di_in_i,
417 drprdy_out => drdy_out_unused_i,
418 drpdo_out => drpdo_out_unused_i,
419 drpwe_in => dwe_in_i,
420 drpaddr_in_lane1 => daddr_in_lane1_i,
421 drpen_in_lane1 => den_in_lane1_i,
422 drpdi_in_lane1 => di_in_lane1_i,
423 drprdy_out_lane1 => drdy_out_lane1_unused_i,
424 drpdo_out_lane1 => drpdo_out_lane1_unused_i,
425 drpwe_in_lane1 => dwe_in_lane1_i,
426 drpaddr_in_lane2 => daddr_in_lane2_i,
427 drpen_in_lane2 => den_in_lane2_i,
428 drpdi_in_lane2 => di_in_lane2_i,
429 drprdy_out_lane2 => drdy_out_lane2_unused_i,
430 drpdo_out_lane2 => drpdo_out_lane2_unused_i,
431 drpwe_in_lane2 => dwe_in_lane2_i,
432 drpaddr_in_lane3 => daddr_in_lane3_i,
433 drpen_in_lane3 => den_in_lane3_i,
434 drpdi_in_lane3 => di_in_lane3_i,
435 drprdy_out_lane3 => drdy_out_lane3_unused_i,
436 drpdo_out_lane3 => drpdo_out_lane3_unused_i,
437 drpwe_in_lane3 => dwe_in_lane3_i,
438  loopback => loopback_i
439 
440  );
441 
442 end Behavioral;
443 
444 
445 
aurora_wrapper_hub2.Behavioral
Definition: aurora_wrapper_hub2.vhd:50
aurora_wrapper_hub2
Definition: aurora_wrapper_hub2.vhd:6
efex_aurora_hub2_support
Definition: efex_aurora_hub2_support.vhd:61
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