xadc_eFEX Entity Reference

Inheritance diagram for xadc_eFEX:

Entities
rtl	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Generics
reg48	bit_vector ( 15 downto 0 ) := x " 0000 "
reg49	bit_vector ( 15 downto 0 ) := x " 0000 "

Ports
DCLK	in	STD_LOGIC
RESET	in	STD_LOGIC
VP	in	STD_LOGIC
VN	in	STD_LOGIC
VAUXP	in	STD_LOGIC_VECTOR ( 5 downto 0 )
VAUXN	in	STD_LOGIC_VECTOR ( 5 downto 0 )
MEASURED_TEMP	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCAUX	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCINT	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCBRAM	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_TEMP_MAX	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_TEMP_MIN	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCAUX_MAX	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCAUX_MIN	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCINT_MAX	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCINT_MIN	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCBRAM_MAX	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_VCCBRAM_MIN	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_2V5	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_1V05	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_1V0	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_3V3	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_1V2	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_1V8	out	STD_LOGIC_VECTOR ( 15 downto 0 )
MEASURED_Vp_Vn	out	STD_LOGIC_VECTOR ( 15 downto 0 )
ALM	out	STD_LOGIC_VECTOR ( 7 downto 0 )
CHANNEL	out	STD_LOGIC_VECTOR ( 4 downto 0 )
OT	out	STD_LOGIC
EOC	out	STD_LOGIC
EOS	out	STD_LOGIC

Detailed Description

Definition at line 41 of file xadc_eFEX.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd