rtl Architecture Reference

Processes
NEXT_STATE_DECODE	( dclk_bufg , RESET )

Types

state_type

( init_read , read_waitdrdy , write_waitdrdy , read_reg00 , reg00_waitdrdy , read_reg01 , reg01_waitdrdy , read_reg02 , reg02_waitdrdy , read_reg03 , reg03_waitdrdy , read_reg06 , reg06_waitdrdy , read_reg10 , reg10_waitdrdy , read_reg11 , reg11_waitdrdy , read_reg12 , reg12_waitdrdy , read_reg13 , reg13_waitdrdy , read_reg14 , reg14_waitdrdy , read_reg15 , reg15_waitdrdy , read_reg20 , reg20_waitdrdy , read_reg21 , reg21_waitdrdy , read_reg22 , reg22_waitdrdy , read_reg23 , reg23_waitdrdy , read_reg24 , reg24_waitdrdy , read_reg25 , reg25_waitdrdy , read_reg26 , reg26_waitdrdy , read_reg27 , reg27_waitdrdy )

Signals
FLOAT_VBRAM_ALARM	STD_LOGIC
FLOAT_MUXADDR	STD_LOGIC_VECTOR ( 4 downto 0 )
den_reg	STD_LOGIC_VECTOR ( 1 downto 0 )
dwe_reg	STD_LOGIC_VECTOR ( 1 downto 0 )
vauxp_active	STD_LOGIC_VECTOR ( 15 downto 0 )
vauxn_active	STD_LOGIC_VECTOR ( 15 downto 0 )
daddr	STD_LOGIC_VECTOR ( 6 downto 0 )
den	STD_LOGIC
di_drp	STD_LOGIC_VECTOR ( 15 downto 0 )
dwe	STD_LOGIC
do_drp	STD_LOGIC_VECTOR ( 15 downto 0 )
drdy	STD_LOGIC
eoc_drp	STD_LOGIC
eos_drp	STD_LOGIC
busy	STD_LOGIC
dclk_bufg	STD_LOGIC
state	state_type
next_state	state_type

Instantiations
u_bufg	bufg
u0	xadc

Detailed Description

Definition at line 79 of file xadc_eFEX.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/xadc_eFEX.vhd