eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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xadc_eFEX.vhd
1 -- Company: Xilinx
2 -- Engineer: Jim Tatsukawa
3 -- Date: 2/10/2014
4 -- Design Name: ug480
5 -- Module Name: ug480.vhd
6 -- Version: 2.1 - Changed read_reg06 DADDR="0000110"
7 -- 2.0 - Initial self contained design
8 -- Target Devices: 7 Series Family
9 -- Tool versions: 2014.1
10 -- Description: This is a basic demonstration of the XADC
11 --
12 -- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
13 -- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
14 -- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
15 -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
16 -- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
17 -- APPLICATION OR STANDARD, XILINX IS MAKING NO
18 -- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
19 -- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
20 -- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
21 -- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
22 -- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
23 -- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
24 -- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
25 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
26 -- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
27 -- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 -- PURPOSE.
29 
30 -- (c) Copyright 2013-2014 Xilinx, Inc.
31 -- All rights reserved.
32 
33 -------------------------------------------------------------------------------
34 
35 library ieee;
36 use ieee.std_logic_1164.all;
37 use ieee.numeric_std.all;
38 Library UNISIM;
39 use UNISIM.VCOMPONENTS.ALL;
40 
41 entity xadc_eFEX is
42 generic ( reg48 : bit_vector(15 downto 0) := x"0000";
43  reg49 : bit_vector(15 downto 0) := x"0000");
44  port
45  (
46  DCLK : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
47  RESET : in STD_LOGIC; -- Reset signal for the System Monitor control logic
48  VP, VN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
49  VAUXP, VAUXN : in STD_LOGIC_VECTOR (5 downto 0);
50  MEASURED_TEMP : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
51  MEASURED_VCCAUX : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
52  MEASURED_VCCINT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
53  MEASURED_VCCBRAM : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
54  MEASURED_TEMP_MAX : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
55  MEASURED_TEMP_MIN : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
56  MEASURED_VCCAUX_MAX : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
57  MEASURED_VCCAUX_MIN : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
58  MEASURED_VCCINT_MAX : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
59  MEASURED_VCCINT_MIN : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
60  MEASURED_VCCBRAM_MAX : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
61  MEASURED_VCCBRAM_MIN : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
62  MEASURED_2V5 : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
63  MEASURED_1V05 : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
64  MEASURED_1V0 : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
65  MEASURED_3V3 : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
66  MEASURED_1V2 : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
67  MEASURED_1V8 : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
68  MEASURED_Vp_Vn : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
69  ALM : out STD_LOGIC_VECTOR (7 downto 0); -- Output data bus for dynamic reconfiguration port
70  CHANNEL : out STD_LOGIC_VECTOR (4 downto 0); -- Output data bus for dynamic reconfiguration port
71  OT : out STD_LOGIC; -- Output data bus for dynamic reconfiguration port
72  EOC : out STD_LOGIC; -- Output data bus for dynamic reconfiguration port
73  EOS : out STD_LOGIC -- Output data bus for dynamic reconfiguration port
74 
75 );
76 end entity xadc_eFEX;
77 
78 
79 architecture rtl of xadc_eFEX is
80 
81  signal FLOAT_VBRAM_ALARM : STD_LOGIC;
82  signal FLOAT_MUXADDR : STD_LOGIC_VECTOR (4 downto 0);
83  signal den_reg, dwe_reg: STD_LOGIC_VECTOR (1 downto 0);
84  signal vauxp_active : STD_LOGIC_VECTOR (15 downto 0);
85  signal vauxn_active : STD_LOGIC_VECTOR (15 downto 0);
86  signal daddr : STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port
87  signal den : STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port
88  signal di_drp : STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port
89  signal dwe : STD_LOGIC; -- Write Enable for the dynamic reconfiguration port
90  signal do_drp : STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
91  signal drdy : STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port
92  signal eoc_drp : STD_LOGIC;
93  signal eos_drp : STD_LOGIC;
94  signal busy : STD_LOGIC; -- ADC Busy signal
95  signal dclk_bufg : STD_LOGIC;
96  type state_type is (init_read, read_waitdrdy,
97  write_waitdrdy,
98  read_reg00,
99  reg00_waitdrdy,
100  read_reg01,
101  reg01_waitdrdy,
102  read_reg02,
103  reg02_waitdrdy,
104  read_reg03,
105  reg03_waitdrdy,
106  read_reg06,
107  reg06_waitdrdy,
108  read_reg10,
109  reg10_waitdrdy,
110  read_reg11,
111  reg11_waitdrdy,
112  read_reg12,
113  reg12_waitdrdy,
114  read_reg13,
115  reg13_waitdrdy,
116  read_reg14,
117  reg14_waitdrdy,
118  read_reg15,
119  reg15_waitdrdy,
120  read_reg20,
121  reg20_waitdrdy,
122  read_reg21,
123  reg21_waitdrdy,
124  read_reg22,
125  reg22_waitdrdy,
126  read_reg23,
127  reg23_waitdrdy,
128  read_reg24,
129  reg24_waitdrdy,
130  read_reg25,
131  reg25_waitdrdy,
132  read_reg26,
133  reg26_waitdrdy,
134  read_reg27,
135  reg27_waitdrdy
136  );
137 
138  signal state, next_state : state_type;
139 
140 begin
141  U_BUFG : BUFG
142  port map(
143  I => DCLK,
144  O => dclk_bufg);
145 
146 
147  U0 : XADC
148  generic map(
149  INIT_40 => X"9000", -- averaging of 16 selected for external channels -- mjs change from 9000 to 91000
150  INIT_41 => X"2ef0", -- Continuous Seq Mode, Disable unused ALMs, Enable calibration
151  INIT_42 => X"0400", -- Set DCLK divides -- rjs: now for ipbus clock at 31.25 MHz, was /4
152  INIT_43 => X"2ef0", -- CONFIG3
153  INIT_46 => X"0001", -- CHSEL0 - enable USER0
154  INIT_47 => X"0000", -- SEQAVG0 disabled
155  INIT_48 => reg48 , --X"4f01", -- CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration
156  INIT_49 => reg49 , --X"050f", -- CHSEL2 - enable aux analog channels 0 - 3 and 8 and 10
157  INIT_4A => X"0000", -- SEQAVG1 disabled
158  INIT_4B => X"0000", -- SEQAVG2 disabled
159  INIT_4C => X"0000", -- SEQINMODE0
160  INIT_4D => X"0000", -- SEQINMODE1
161  INIT_4E => X"0000", -- SEQACQ0
162  INIT_4F => X"0000", -- SEQACQ1
163  INIT_50 => X"b5ed", -- Temp upper alarm trigger 85C
164  INIT_51 => X"5999", -- Vccint upper alarm limit 1.05V
165  INIT_52 => X"A147", -- Vccaux upper alarm limit 1.89V
166  INIT_53 => X"dddd", -- OT upper alarm limit 125C - see Thermal Management
167  INIT_54 => X"a93a", -- Temp lower alarm reset 60C
168  INIT_55 => X"5111", -- Vccint lower alarm limit 0.95V
169  INIT_56 => X"91Eb", -- Vccaux lower alarm limit 1.71V
170  INIT_57 => X"ae4e", -- OT lower alarm reset 70C - see Thermal Management
171  INIT_58 => X"5999", -- VCCBRAM upper alarm limit 1.05V
172  SIM_MONITOR_FILE => "design.txt"
173  )
174 
175 port map (
176  CONVST => '0',
177  CONVSTCLK => '0',
178  DADDR => daddr,
179  DCLK => dclk_bufg,
180  DEN => den_reg(0),
181  DI(15 downto 0) => di_drp,
182  DWE => dwe_reg(0),
183  RESET => RESET,
184  VAUXN(15 downto 0) => vauxn_active ,
185  VAUXP(15 downto 0) => vauxp_active ,
186  ALM => ALM,
187  BUSY => busy,
188  CHANNEL => CHANNEL,
189  DO(15 downto 0) => do_drp,
190  DRDY => drdy,
191  EOC => eoc_drp,
192  EOS => eos_drp,
193  JTAGBUSY => open,
194  JTAGLOCKED => open,
195  JTAGMODIFIED => open,
196  OT => OT,
197  MUXADDR => open,
198  VN => Vn,
199  VP => Vp
200  );
201  vauxp_active <= "00000" & VAUXP(5) & '0' & VAUXP(4) &"0000" & VAUXP(3 downto 0) ; --"0000010100001111";
202  vauxn_active <= "00000" & VAUXN(5) & '0' & VAUXN(4) &"0000" & VAUXN(3 downto 0) ; --"0000010100001111";
203  EOC <= eoc_drp;
204  EOS <= eos_drp;
205 
206 
207  NEXT_STATE_DECODE: process (dclk_bufg, RESET)
208  begin
209  if (RESET = '1') then
210  state <= init_read;
211  elsif (dclk_bufg'event and dclk_bufg = '1') then
212  case (state) is
213  when init_read =>
214  daddr <= "1000000";
215  den_reg <= "10";
216  dwe_reg <= "00"; -- performing read
217  state <= read_waitdrdy;
218  when read_waitdrdy =>
219  if eos_drp = '1' then
220  state <= write_waitdrdy;
221  di_drp <= do_drp AND "0000001111111111"; --Clearing AVG bits for Configreg0
222  daddr <= "1000000";
223  den_reg <= "10";
224  dwe_reg <= "10"; -- performing write
225  else
226  state <= read_waitdrdy;
227  den_reg <= "0" & den_reg(1) ;
228  dwe_reg <= "0" & dwe_reg(1) ;
229  end if;
230  when write_waitdrdy =>
231  if drdy = '1' then
232  state <= read_reg00;
233  den_reg <= den_reg;
234  dwe_reg <= dwe_reg; --performing write
235  else
236  den_reg <= "0" & den_reg(1) ;
237  dwe_reg <= "0" & dwe_reg(1) ;
238  state <= write_waitdrdy;
239  end if;
240  when read_reg00 =>
241  daddr <= "0000000";
242  den_reg <= "10";
243  state <= reg00_waitdrdy;
244  when reg00_waitdrdy =>
245  if eos_drp = '1' then
246  MEASURED_TEMP <= do_drp;
247  den_reg <= den_reg;
248  dwe_reg <= dwe_reg;
249  state <= read_reg01;
250  else
251  den_reg <= "0" & den_reg(1) ;
252  dwe_reg <= "0" & dwe_reg(1) ;
253  state <= reg00_waitdrdy;
254  end if;
255 
256  when read_reg01 =>
257  daddr <= "0000001";
258  den_reg <= "10";
259  state <= reg01_waitdrdy;
260  when reg01_waitdrdy =>
261  if drdy = '1' then
262  MEASURED_VCCINT <= do_drp;
263  den_reg <= den_reg;
264  state <= read_reg02;
265  else
266  den_reg <= "0" & den_reg(1) ;
267  state <= reg01_waitdrdy ;
268  end if;
269 
270  when read_reg02 =>
271  daddr <= "0000010";
272  den_reg <= "10";
273  state <= reg02_waitdrdy;
274  when reg02_waitdrdy =>
275  if drdy = '1' then
276  state <= read_reg03;
277  MEASURED_VCCAUX <= do_drp;
278  den_reg <= den_reg;
279  else
280  state <= reg02_waitdrdy ;
281  den_reg <= "0" & den_reg(1) ;
282  end if;
283 
284  when read_reg03 =>
285  daddr <= "0000011";
286  den_reg <= "10";
287  state <= reg03_waitdrdy;
288  when reg03_waitdrdy =>
289  if drdy = '1' then
290  state <= read_reg06;
291  MEASURED_Vp_Vn <= do_drp;
292  den_reg <= den_reg;
293  else
294  state <= reg03_waitdrdy ;
295  den_reg <= "0" & den_reg(1) ;
296  end if;
297 
298 
299  when read_reg06 =>
300  daddr <= "0000110";
301  den_reg <= "10";
302  state <= reg06_waitdrdy;
303  when reg06_waitdrdy =>
304  if drdy = '1' then
305  state <= read_reg10;
306  MEASURED_VCCBRAM <= do_drp;
307  den_reg <= den_reg;
308  else
309  den_reg <= "0" & den_reg(1) ;
310  state <= reg06_waitdrdy ;
311  end if;
312 
313  when read_reg10 =>
314  daddr <= "0010000";
315  den_reg <= "10";
316  state <= reg10_waitdrdy;
317  when reg10_waitdrdy =>
318  if drdy = '1' then
319  state <= read_reg11;
320  MEASURED_2V5 <= do_drp;
321  den_reg <= den_reg;
322  else
323  den_reg <= "0" & den_reg(1) ;
324  state <= reg10_waitdrdy ;
325  end if;
326 
327  when read_reg11 =>
328  daddr <= "0011000";
329  den_reg <= "10";
330  state <= reg11_waitdrdy;
331  when reg11_waitdrdy =>
332  if drdy = '1' then
333  state <= read_reg12;
334  MEASURED_1V05 <= do_drp;
335  den_reg <= den_reg;
336  else
337  den_reg <= "0" & den_reg(1) ;
338  state <= reg11_waitdrdy ;
339  end if;
340 
341  when read_reg12 =>
342  daddr <= "0010001";
343  den_reg <= "10";
344  state <= reg12_waitdrdy;
345  when reg12_waitdrdy =>
346  if drdy = '1' then
347  state <= read_reg13;
348  MEASURED_1V0 <= do_drp;
349  den_reg <= den_reg;
350  else
351  den_reg <= "0" & den_reg(1) ;
352  state <= reg12_waitdrdy ;
353  end if;
354 
355  when read_reg13 =>
356  daddr <= "0011010";
357  den_reg <= "10";
358  state <= reg13_waitdrdy;
359  when reg13_waitdrdy =>
360  if drdy = '1' then
361  state <= read_reg14;
362  MEASURED_3V3 <= do_drp;
363  den_reg <= den_reg;
364  else
365  den_reg <= "0" & den_reg(1) ;
366  state <= reg13_waitdrdy ;
367  end if;
368 
369  when read_reg14 =>
370  daddr <= "0010011";
371  den_reg <= "10";
372  state <= reg14_waitdrdy;
373  when reg14_waitdrdy =>
374  if drdy = '1' then
375  state <= read_reg15;
376  MEASURED_1V2 <= do_drp;
377  den_reg <= den_reg;
378  else
379  den_reg <= "0" & den_reg(1) ;
380  state <= reg14_waitdrdy ;
381  end if;
382 
383  when read_reg15 =>
384  daddr <= "0010010";
385  den_reg <= "10";
386  state <= reg15_waitdrdy;
387  when reg15_waitdrdy =>
388  if drdy = '1' then
389  state <= read_reg20;
390  MEASURED_1V8 <= do_drp;
391  den_reg <= den_reg;
392  else
393  den_reg <= "0" & den_reg(1) ;
394  state <= reg15_waitdrdy ;
395  end if;
396 
397  when read_reg20 => -- FIXME wrap below (maybe above too) in a for-loop
398  daddr <= "0100000";
399  den_reg <= "10";
400  state <= reg20_waitdrdy;
401  when reg20_waitdrdy =>
402  if drdy = '1' then
403  MEASURED_TEMP_MAX <= do_drp;
404  den_reg <= den_reg;
405  state <= read_reg21;
406  else
407  den_reg <= "0" & den_reg(1) ;
408  state <= reg20_waitdrdy ;
409  end if;
410 
411  when read_reg21 =>
412  daddr <= "0100001";
413  den_reg <= "10";
414  state <= reg21_waitdrdy;
415  when reg21_waitdrdy =>
416  if drdy = '1' then
417  MEASURED_VCCINT_MAX <= do_drp;
418  den_reg <= den_reg;
419  state <= read_reg22;
420  else
421  state <= reg21_waitdrdy ;
422  den_reg <= "0" & den_reg(1) ;
423  end if;
424 
425  when read_reg22 =>
426  daddr <= "0100010";
427  den_reg <= "10";
428  state <= reg22_waitdrdy;
429  when reg22_waitdrdy =>
430  if drdy = '1' then
431  MEASURED_VCCAUX_MAX <= do_drp;
432  den_reg <= den_reg;
433  state <= read_reg23;
434  else
435  den_reg <= "0" & den_reg(1) ;
436  state <= reg22_waitdrdy ;
437  end if;
438 
439  when read_reg23 =>
440  daddr <= "0100011";
441  den_reg <= "10";
442  state <= reg23_waitdrdy;
443  when reg23_waitdrdy =>
444  if drdy = '1' then
445  state <= read_reg24;
446  MEASURED_VCCBRAM_MAX <= do_drp;
447  den_reg <= den_reg;
448  else
449  state <= reg23_waitdrdy ;
450  den_reg <= "0" & den_reg(1) ;
451  end if;
452 
453  when read_reg24 =>
454  daddr <= "0100100";
455  den_reg <= "10";
456  state <= reg24_waitdrdy;
457  when reg24_waitdrdy =>
458  if drdy = '1' then
459  MEASURED_TEMP_MIN <= do_drp;
460  den_reg <= den_reg;
461  state <= read_reg25;
462  else
463  den_reg <= "0" & den_reg(1) ;
464  state <= reg24_waitdrdy ;
465  end if;
466 
467  when read_reg25 =>
468  daddr <= "0100101";
469  den_reg <= "10";
470  state <= reg25_waitdrdy;
471  when reg25_waitdrdy =>
472  if drdy = '1' then
473  MEASURED_VCCINT_MIN <= do_drp;
474  den_reg <= den_reg;
475  state <= read_reg26;
476  else
477  state <= reg25_waitdrdy ;
478  den_reg <= "0" & den_reg(1) ;
479  end if;
480 
481  when read_reg26 =>
482  daddr <= "0100110";
483  den_reg <= "10";
484  state <= reg26_waitdrdy;
485  when reg26_waitdrdy =>
486  if drdy = '1' then
487  MEASURED_VCCAUX_MIN <= do_drp;
488  den_reg <= den_reg;
489  state <= read_reg27;
490  else
491  den_reg <= "0" & den_reg(1) ;
492  state <= reg26_waitdrdy ;
493  end if;
494 
495  when read_reg27 =>
496  daddr <= "0100111";
497  den_reg <= "10";
498  state <= reg27_waitdrdy;
499  when reg27_waitdrdy =>
500  if drdy = '1' then
501  state <= read_reg00;
502  MEASURED_VCCBRAM_MIN <= do_drp;
503  den_reg <= den_reg;
504  else
505  state <= reg27_waitdrdy ;
506  den_reg <= "0" & den_reg(1) ;
507  end if;
508 
509  when others =>
510  state <= init_read ;
511  end case;
512  end if;
513  end process;
514 
515 
516 end rtl;
xadc_eFEX.rtl
Definition: xadc_eFEX.vhd:79
xadc_eFEX
Definition: xadc_eFEX.vhd:41
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