testbench Architecture Reference

Processes
WaveGen_Proc	( )
set_error	( )
Check_crc	( )
random_data	( )
WaveGen_Proc	( )

Constants
REVERSE_BIT_ORDER	boolean := TRUE
clk_period	time := 10 ns
DELAY	time := 2 ns

Signals
data_in	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
tx_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
rx_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
rx_errors	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
start_txcrc	std_logic := ' 0 '
crc_out	std_logic_vector ( 8 downto 0 )
crc23_out	std_logic_vector ( 8 downto 0 )
rx_crc	std_logic_vector ( 8 downto 0 )
crc_error	std_logic := ' 0 '
end_of_frame	std_logic := ' 0 '
start_rxcrc	std_logic := ' 0 '
clock	std_logic := ' 1 '
rand_num	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
rand_num1	integer := 0
rand_num2	integer := 0
tx_data1	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
tx_data2	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
data_out1	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
data_out2	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
inv_crc_out	std_logic_vector ( 8 downto 0 )
rx_crc1	std_logic_vector ( 8 downto 0 )
rx_crc2	std_logic_vector ( 8 downto 0 )

Instantiations
tx	osum_crc9d32 <Entity osum_crc9d32>
crc9d23_i	osum_crc9d23 <Entity osum_crc9d23>
append_crc	crc_add <Entity crc_add>
rx	osum_crc9d32 <Entity osum_crc9d32>
tx	crc9d32 <Entity crc9d32>
append1	crc_add <Entity crc_add>
rx1	crc9d32 <Entity crc9d32>
append2	crc_add <Entity crc_add>
rx2	crc9d32 <Entity crc9d32>

Member Function Documentation

Check_crc()

Check_crc ( )

Process

random_data()

random_data ( )

Process

set_error()

set_error ( )

Process

WaveGen_Proc() [1/2]

WaveGen_Proc

(

)

WaveGen_Proc() [2/2]

WaveGen_Proc

(

)

Member Data Documentation

append1

append1 crc_add

Instantiation

append2

append2 crc_add

Instantiation

append_crc

append_crc crc_add

Instantiation

clk_period

clk_period time := 10 ns

Constant

clock

clock std_logic := ' 1 '

Signal

crc23_out

crc23_out std_logic_vector ( 8 downto 0 )

Signal

crc9d23_i

crc9d23_i osum_crc9d23

Instantiation

crc_error

crc_error std_logic := ' 0 '

Signal

crc_out

crc_out std_logic_vector ( 8 downto 0 )

Signal

data_in

data_in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

data_out1

data_out1 std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

data_out2

data_out2 std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

DELAY

DELAY time := 2 ns

Constant

end_of_frame

end_of_frame std_logic := ' 0 '

Signal

inv_crc_out

inv_crc_out std_logic_vector ( 8 downto 0 )

Signal

rand_num

rand_num std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

rand_num1

rand_num1 integer := 0

Signal

rand_num2

rand_num2 integer := 0

Signal

REVERSE_BIT_ORDER

REVERSE_BIT_ORDER boolean := TRUE

Constant

rx

rx osum_crc9d32

Instantiation

rx1

rx1 crc9d32

Instantiation

rx2

rx2 crc9d32

Instantiation

rx_crc

rx_crc std_logic_vector ( 8 downto 0 )

Signal

rx_crc1

rx_crc1 std_logic_vector ( 8 downto 0 )

Signal

rx_crc2

rx_crc2 std_logic_vector ( 8 downto 0 )

Signal

rx_data

rx_data std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

rx_errors

rx_errors std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

start_rxcrc

start_rxcrc std_logic := ' 0 '

Signal

start_txcrc

start_txcrc std_logic := ' 0 '

Signal

tx [1/2]

tx crc9d32

Instantiation

tx [2/2]

tx osum_crc9d32

Instantiation

tx_data

tx_data std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

tx_data1

tx_data1 std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

tx_data2

tx_data2 std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

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The documentation for this class was generated from the following file:

• common/LatomeCRC/sim/crc_tb.vhd