rtl Architecture Reference

Signals
rx_data	std_logic_vector ( 31 downto 0 )
tx_data	std_logic_vector ( 31 downto 0 )
rx_ready	std_logic
rx_next	std_logic
tx_we	std_logic
tx_hdr	std_logic
tx_err	std_logic
cfg_we	std_logic
cfg_addr	std_logic_vector ( 1 downto 0 )
cfg_din	std_logic_vector ( 31 downto 0 )
cfg_dout	std_logic_vector ( 31 downto 0 )

Instantiations
iface	transactor_if <Entity transactor_if>
sm	transactor_sm <Entity transactor_sm>
cfg	transactor_cfg <Entity transactor_cfg>
iface	transactor_if <Entity transactor_if>
sm	transactor_sm <Entity transactor_sm>
cfg	transactor_cfg <Entity transactor_cfg>
iface	transactor_if <Entity transactor_if>
sm	transactor_sm <Entity transactor_sm>
cfg	transactor_cfg <Entity transactor_cfg>

Member Data Documentation

cfg [1/3]

cfg transactor_cfg

Instantiation

cfg [2/3]

cfg transactor_cfg

Instantiation

cfg [3/3]

cfg transactor_cfg

Instantiation

cfg_addr

cfg_addr std_logic_vector ( 1 downto 0 )

Signal

cfg_din

cfg_din std_logic_vector ( 31 downto 0 )

Signal

cfg_dout

cfg_dout std_logic_vector ( 31 downto 0 )

Signal

cfg_we

cfg_we std_logic

Signal

iface [1/3]

iface transactor_if

Instantiation

iface [2/3]

iface transactor_if

Instantiation

iface [3/3]

iface transactor_if

Instantiation

rx_data

rx_data std_logic_vector ( 31 downto 0 )

Signal

rx_next

rx_next std_logic

Signal

rx_ready

rx_ready std_logic

Signal

sm [1/3]

sm transactor_sm

Instantiation

sm [2/3]

sm transactor_sm

Instantiation

sm [3/3]

sm transactor_sm

Instantiation

tx_data

tx_data std_logic_vector ( 31 downto 0 )

Signal

tx_err

tx_err std_logic

Signal

tx_hdr

tx_hdr std_logic

Signal

tx_we

tx_we std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/transactor.vhd