rtl Architecture Reference

Processes
retime_shelf_num	( ttc_clk , tx_shelf_num )
l1id_count	( ttc_clk , L1A )
ecrid_count	( ttc_clk , L1A )
register_l1id	( ttc_clk , ecrid , l1id )
delay_stuff	( data_clk , eof )
ttc_mux	( data_clk )

Constants
REVERSE_BIT_ORDER	boolean := TRUE

Signals
ttcinfo	mgt_data_array ( 3 downto 0 )
ttcreg	mgt_data_array ( 3 downto 0 )
eof	std_logic
start_crc	std_logic
crc9	std_logic_vector ( 8 downto 0 )
crc9d32	std_logic_vector ( 8 downto 0 )
ttcregdel	mgt_data
ttc_crc	mgt_data
shelf_num	std_logic_vector ( 3 downto 0 )
l1a_count	unsigned ( 23 downto 0 ) := ( others = > ' 0 ' )
l1id	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
ecr_count	unsigned ( 7 downto 0 ) := ( others = > ' 0 ' )
ecrid	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ecr_reset	std_logic := ' 0 '

Instantiations
framer	framing_sync_logic <Entity framing_sync_logic>
crc32	osum_crc9d32 <Entity osum_crc9d32>
crc23	osum_crc9d23 <Entity osum_crc9d23>

Member Function Documentation

delay_stuff()

delay_stuff (   data_clk ,   eof   )

Process

ecrid_count()

ecrid_count (   ttc_clk ,   L1A   )

Process

l1id_count()

l1id_count	(		ttc_clk,
			L1A
	)

register_l1id()

register_l1id (   ttc_clk ,   ecrid ,   l1id   )

Process

retime_shelf_num()

retime_shelf_num (   ttc_clk ,   tx_shelf_num   )

Process

ttc_mux()

ttc_mux

(

data_clk

)

Member Data Documentation

crc23

crc23 osum_crc9d23

Instantiation

crc32

crc32 osum_crc9d32

Instantiation

crc9

crc9 std_logic_vector ( 8 downto 0 )

Signal

crc9d32

crc9d32 std_logic_vector ( 8 downto 0 )

Signal

ecr_count

ecr_count unsigned ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

ecr_reset

ecr_reset std_logic := ' 0 '

Signal

ecrid

ecrid std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )

Signal

eof

eof std_logic

Signal

framer

framer framing_sync_logic

Instantiation

l1a_count

l1a_count unsigned ( 23 downto 0 ) := ( others = > ' 0 ' )

Signal

l1id

l1id std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )

Signal

REVERSE_BIT_ORDER

REVERSE_BIT_ORDER boolean := TRUE

Constant

shelf_num

shelf_num std_logic_vector ( 3 downto 0 )

Signal

start_crc

start_crc std_logic

Signal

ttc_crc

ttc_crc mgt_data

Signal

ttcinfo

ttcinfo mgt_data_array ( 3 downto 0 )

Signal

ttcreg

ttcreg mgt_data_array ( 3 downto 0 )

Signal

ttcregdel

ttcregdel mgt_data

Signal

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The documentation for this class was generated from the following file:

• FTM/Control/hdl/ttcinfo_source.vhd