TOP_LEVEL Architecture Reference

Processes
PROCESS_256	( gtx_clk )
regrx	( gtx_clk )
PROCESS_817	( gtx_clk )
regrx	( gtx_clk )

Components
v6_emac_v2_3_sgmii
v6_gtxwizard_top	<Entity v6_gtxwizard_top>
sync_block	<Entity sync_block>
reset_sync	<Entity reset_sync>

Signals
gmii_txd_int	std_logic_vector ( 7 downto 0 )
gmii_rx_dv_int	std_logic
gmii_rxd_int	std_logic_vector ( 7 downto 0 )
plllock_i	std_logic
emac_locked_i	std_logic
mgt_rx_data_i	std_logic_vector ( 7 downto 0 )
signal_detect_i	std_logic
rxelecidle_i	std_logic
resetdone_i	std_logic
encommaalign_i	std_logic
loopback_i	std_logic
mgt_rx_reset_i	std_logic
mgt_tx_reset_i	std_logic
powerdown_i	std_logic
rxclkcorcnt_i	std_logic_vector ( 2 downto 0 )
rxchariscomma_i	std_logic
rxcharisk_i	std_logic
rxdisperr_i	std_logic
rxnotintable_i	std_logic
rxrundisp_i	std_logic
txbuferr_i	std_logic
txchardispmode_i	std_logic
txchardispval_i	std_logic
txcharisk_i	std_logic
rxbufstatus_i	std_logic
rxchariscomma_r	std_logic
rxcharisk_r	std_logic
rxclkcorcnt_r	std_logic_vector ( 2 downto 0 )
rxdisperr_r	std_logic
rxnotintable_r	std_logic
rxrundisp_r	std_logic
txchardispmode_r	std_logic
txchardispval_r	std_logic
txcharisk_r	std_logic
mgt_tx_data_r	std_logic_vector ( 7 downto 0 )
speedis10100_int	std_logic
tx_axi_clk_out	std_logic
rx_mac_aclk_int	std_logic
tx_mac_aclk_int	std_logic
glbl_rst	std_logic
gtx_reset_in	std_logic
gtx_clk_reset_int	std_logic
gtx_pre_resetn	std_logic := ' 0 '
gtx_reset	std_logic := ' 1 '
gtx_resetn	std_logic := ' 0 '
tx_reset_int	std_logic
rx_reset_int	std_logic
rx_statistics_vector_int	std_logic_vector ( 27 downto 0 )
rx_statistics_valid_int	std_logic
tx_statistics_vector_int	std_logic_vector ( 31 downto 0 )
tx_statistics_valid_int	std_logic

Attributes
keep	string
keep	tx_mac_aclk_int : signal is " true "
keep	rx_mac_aclk_int : signal is " true "
keep	gmii_rxd_int : signal is " true "
keep	rxchariscomma_r : signal is " true "
keep	rxcharisk_r : signal is " true "
keep	rxclkcorcnt_r : signal is " true "
keep	rxdisperr_r : signal is " true "
keep	rxnotintable_r : signal is " true "
keep	rxrundisp_r : signal is " true "
ASYNC_REG	string
ASYNC_REG	gtx_pre_resetn : signal is " TRUE "
ASYNC_REG	gtx_resetn : signal is " TRUE "
keep	gtx_resetn : signal is " TRUE "

Instantiations
gtx_reset_gen	reset_sync <Entity reset_sync>
v6_gtxwizard_top_inst	v6_gtxwizard_top <Entity v6_gtxwizard_top>
v6emac_core	v6_emac_v2_3_sgmii
gtx_reset_gen	reset_sync <Entity reset_sync>
v6_gtxwizard_top_inst	v6_gtxwizard_top <Entity v6_gtxwizard_top>
v6emac_core	v6_emac_v2_3_sgmii

Member Function Documentation

PROCESS_256()

PROCESS_256

(

gtx_clk

)

PROCESS_817()

PROCESS_817

(

gtx_clk

)

regrx() [1/2]

regrx

(

gtx_clk

)

regrx() [2/2]

regrx

(

gtx_clk

)

Member Data Documentation

ASYNC_REG [1/3]

ASYNC_REG string

Attribute

ASYNC_REG [2/3]

ASYNC_REG gtx_pre_resetn : signal is " TRUE "

Attribute

ASYNC_REG [3/3]

ASYNC_REG gtx_resetn : signal is " TRUE "

Attribute

emac_locked_i

emac_locked_i std_logic

Signal

encommaalign_i

encommaalign_i std_logic

Signal

glbl_rst

glbl_rst std_logic

Signal

gmii_rx_dv_int

gmii_rx_dv_int std_logic

Signal

gmii_rxd_int

gmii_rxd_int std_logic_vector ( 7 downto 0 )

Signal

gmii_txd_int

gmii_txd_int std_logic_vector ( 7 downto 0 )

Signal

gtx_clk_reset_int

gtx_clk_reset_int std_logic

Signal

gtx_pre_resetn

gtx_pre_resetn std_logic := ' 0 '

Signal

gtx_reset

gtx_reset std_logic := ' 1 '

Signal

gtx_reset_gen [1/2]

gtx_reset_gen reset_sync

Instantiation

gtx_reset_gen [2/2]

gtx_reset_gen reset_sync

Instantiation

gtx_reset_in

gtx_reset_in std_logic

Signal

gtx_resetn

gtx_resetn std_logic := ' 0 '

Signal

keep [1/11]

keep string

Attribute

keep [2/11]

keep tx_mac_aclk_int : signal is " true "

Attribute

keep [3/11]

keep rx_mac_aclk_int : signal is " true "

Attribute

keep [4/11]

keep gmii_rxd_int : signal is " true "

Attribute

keep [5/11]

keep rxchariscomma_r : signal is " true "

Attribute

keep [6/11]

keep rxcharisk_r : signal is " true "

Attribute

keep [7/11]

keep rxclkcorcnt_r : signal is " true "

Attribute

keep [8/11]

keep rxdisperr_r : signal is " true "

Attribute

keep [9/11]

keep rxnotintable_r : signal is " true "

Attribute

keep [10/11]

keep rxrundisp_r : signal is " true "

Attribute

keep [11/11]

keep gtx_resetn : signal is " TRUE "

Attribute

loopback_i

loopback_i std_logic

Signal

mgt_rx_data_i

mgt_rx_data_i std_logic_vector ( 7 downto 0 )

Signal

mgt_rx_reset_i

mgt_rx_reset_i std_logic

Signal

mgt_tx_data_r

mgt_tx_data_r std_logic_vector ( 7 downto 0 )

Signal

mgt_tx_reset_i

mgt_tx_reset_i std_logic

Signal

plllock_i

plllock_i std_logic

Signal

powerdown_i

powerdown_i std_logic

Signal

reset_sync

reset_sync

Component

resetdone_i

resetdone_i std_logic

Signal

rx_mac_aclk_int

rx_mac_aclk_int std_logic

Signal

rx_reset_int

rx_reset_int std_logic

Signal

rx_statistics_valid_int

rx_statistics_valid_int std_logic

Signal

rx_statistics_vector_int

rx_statistics_vector_int std_logic_vector ( 27 downto 0 )

Signal

rxbufstatus_i

rxbufstatus_i std_logic

Signal

rxchariscomma_i

rxchariscomma_i std_logic

Signal

rxchariscomma_r

rxchariscomma_r std_logic

Signal

rxcharisk_i

rxcharisk_i std_logic

Signal

rxcharisk_r

rxcharisk_r std_logic

Signal

rxclkcorcnt_i

rxclkcorcnt_i std_logic_vector ( 2 downto 0 )

Signal

rxclkcorcnt_r

rxclkcorcnt_r std_logic_vector ( 2 downto 0 )

Signal

rxdisperr_i

rxdisperr_i std_logic

Signal

rxdisperr_r

rxdisperr_r std_logic

Signal

rxelecidle_i

rxelecidle_i std_logic

Signal

rxnotintable_i

rxnotintable_i std_logic

Signal

rxnotintable_r

rxnotintable_r std_logic

Signal

rxrundisp_i

rxrundisp_i std_logic

Signal

rxrundisp_r

rxrundisp_r std_logic

Signal

signal_detect_i

signal_detect_i std_logic

Signal

speedis10100_int

speedis10100_int std_logic

Signal

sync_block

sync_block

Component

tx_axi_clk_out

tx_axi_clk_out std_logic

Signal

tx_mac_aclk_int

tx_mac_aclk_int std_logic

Signal

tx_reset_int

tx_reset_int std_logic

Signal

tx_statistics_valid_int

tx_statistics_valid_int std_logic

Signal

tx_statistics_vector_int

tx_statistics_vector_int std_logic_vector ( 31 downto 0 )

Signal

txbuferr_i

txbuferr_i std_logic

Signal

txchardispmode_i

txchardispmode_i std_logic

Signal

txchardispmode_r

txchardispmode_r std_logic

Signal

txchardispval_i

txchardispval_i std_logic

Signal

txchardispval_r

txchardispval_r std_logic

Signal

txcharisk_i

txcharisk_i std_logic

Signal

txcharisk_r

txcharisk_r std_logic

Signal

v6_emac_v2_3_sgmii

v6_emac_v2_3_sgmii

Component

v6_gtxwizard_top

v6_gtxwizard_top

Component

v6_gtxwizard_top_inst [1/2]

v6_gtxwizard_top_inst v6_gtxwizard_top

Instantiation

v6_gtxwizard_top_inst [2/2]

v6_gtxwizard_top_inst v6_gtxwizard_top

Instantiation

v6emac_core [1/2]

v6emac_core v6_emac_v2_3_sgmii

Instantiation

v6emac_core [2/2]

v6emac_core v6_emac_v2_3_sgmii

Instantiation

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v6_emac_v2_3_sgmii/v6_emac_v2_3_sgmii_block.vhd