ttc_chan_regs.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.10.2019 18:51:12
-- Design Name: 
-- Module Name: ttc_chan_regs - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.ipbus.all;
use work.ipbus_decode_L1CaloHubRodTTCRegisters.all;
 
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ttc_chan_regs is
    Port ( 
    ipb_clk                 : in std_logic;
    ipb_rst                 : in std_logic;
    ipb_in                  : in ipb_wbus;
    ipb_out                 : out ipb_rbus;
    
    pp_clock                : in std_logic;
    clk_125                 : in std_logic;
--    time_count              : in STD_LOGIC_VECTOR (31 downto 0);   --synchronous to the pp_clock 
    ttc_chan_stat           : in STD_LOGIC_VECTOR (31 downto 0);
    ttc_fifo_level          : in STD_LOGIC_VECTOR (15 downto 0);  --synchronous to the pp_clock
    L1ID_error              : in std_logic;
    CTTC_CRC_error          : in std_logic;
    cttc_user_clk           : in std_logic;
    seq                     : in STD_LOGIC_VECTOR(1 DOWNTO 0);
    L1A                     : in std_logic;
    ttc_reset               : out std_logic;
    hub_link_reset          : out std_logic;
    ttc_ignore              : out std_logic;
    TTC_CRC_ignore          : out std_logic;
    TTC_fifo_rst            : out std_logic;
    header_sequence         : out STD_LOGIC_VECTOR (11 downto 0);  
    header_type             : out STD_LOGIC_VECTOR (3 downto 0);
    det_spec_evnt_sel       : out STD_LOGIC_VECTOR (3 downto 0);
    ttc_reg                 : in STD_LOGIC_VECTOR(63 DOWNTO 0);
    event_sel                : out STD_LOGIC_VECTOR (2 downto 0);
    event_count              : in STD_LOGIC_VECTOR(31 DOWNTO 0);
    orbit_count              : in STD_LOGIC_VECTOR(15 DOWNTO 0);
    flx_backpressure         : in std_logic_vector(11 downto 0);
    event_count_reset        : out std_logic;
    orbit_count_reset        : out std_logic;
    bcn_adjustment           : out std_logic_vector(11 downto 0);
    
    l1id_continuity_control  : out std_logic_vector(31 downto 0);
    l1id_continuity_status   : in STD_LOGIC_vector (31 downto 0);
    l1id_local_miss          : in STD_LOGIC_vector (31 downto 0);
    l1id_ttc_miss            : in STD_LOGIC_vector (31 downto 0);
    l1id_error_count         : in STD_LOGIC_vector (31 downto 0);
    timeout_threshold        : out std_logic_vector(31 downto 0);
    repeat_counter           : in  STD_LOGIC_vector(31 downto 0)
    
    );
end ttc_chan_regs;
 
architecture RTL of ttc_chan_regs is
 
COMPONENT ttc_regs_ila
 
PORT (
    clk : IN STD_LOGIC;
    probe0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); 
    probe1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
    probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe4 : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT  ;
 
 
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
 
signal    ttc_rst_stb               : std_logic;
signal    ttc_reset_reg                 : std_logic_vector (31 downto 0);
signal    ttc_rst_rst               : std_logic;
signal    ccc_rst_stb               : std_logic;
signal    ccc_rst_rst               : std_logic;
 
signal    ttc_fifo_control          : std_logic_vector (31 downto 0);
signal    TTC_fifo_status           : std_logic_vector (31 downto 0);
signal    TTC_fifo_fill_level       : std_logic_vector (31 downto 0);
signal    TTC_fifo_busy_Count       : std_logic_vector (31 downto 0); 
signal    ttc_fifo_busy_threshold   : STD_LOGIC_VECTOR (31 downto 0);
signal    CTTC_link_status          : STD_LOGIC_VECTOR (31 downto 0);
 
signal    BCN  : STD_LOGIC_VECTOR (31 downto 0);
signal    L1ID : STD_LOGIC_VECTOR (23 downto 0);
signal    ECRID : STD_LOGIC_VECTOR (7 downto 0);
signal    rxdisperr            : std_logic;   
signal    rxnotintable         : std_logic;    
signal    rxresetdone          : std_logic;                   
signal    cpllfbclklost        : std_logic;   
signal    cplllock              : std_logic;                           
signal    rxfsmresetdone        : std_logic;  
signal    cpllrefclklost        : std_logic; 
signal    disp_err_count        : STD_LOGIC_VECTOR (7 downto 0);
signal    table_err_count       : STD_LOGIC_VECTOR (7 downto 0);
signal    crc_error_count       : STD_LOGIC_VECTOR (7 downto 0);
 
signal    ttc_watermark_reset   : std_logic;
signal    ttc_watermark         : std_logic_vector (15 downto 0);
signal    ttc_control           : std_logic_vector (31 downto 0);
signal    pkt_hdr_info          : std_logic_vector (31 downto 0);
 
signal    run_event_count_reset : std_logic;
signal    event_count_reset_i   : std_logic;
signal    orbit_count_reset_i   : std_logic;
signal    run_event_count       : std_logic_vector (35 downto 0);
signal    bcn_adjust_i         : std_logic_vector(31 downto 0);
signal    cpll_lock_delay_1     : std_logic;
signal    cpll_lock_delay_2     : std_logic;
signal    cpll_lock_lost        : std_logic;
 
begin
 
  fabric: entity work.ipbus_fabric_sel
  generic map(
    NSLV => N_SLAVES,
    SEL_WIDTH => IPBUS_SEL_WIDTH)
  port map(
    ipb_in => ipb_in,
    ipb_out => ipb_out,
    sel => ipbus_sel_L1CaloHubRodTTCRegisters(ipb_in.ipb_addr),
    ipb_to_slaves => ipbw,
    ipb_from_slaves => ipbr
  );
 
 
 BCN(11 downto 0)  <=  ttc_reg(11 downto 0);
 BCN(31 downto 12) <= (others => '0');
 L1ID <=  ttc_reg(35 downto 12);
ECRID <=  ttc_reg(43 downto 36);
 
 
cpllrefclklost <= ttc_chan_stat(6);
rxdisperr <= ttc_chan_stat(5);       
rxnotintable <= ttc_chan_stat(4);     
rxresetdone <= ttc_chan_stat(3);                     
cpllfbclklost <= ttc_chan_stat(2);                      
cplllock  <=  ttc_chan_stat(1);                           
rxfsmresetdone <= ttc_chan_stat(0);   
 
 
process (clk_125) begin   --sample with clk125 because it's independent of potentially failing ro_user_clk
    if rising_edge (clk_125) then
       cpll_lock_delay_1 <= cplllock;
       cpll_lock_delay_2 <= cpll_lock_delay_1;
    end if;
end process;       
 
process (clk_125) begin   --sample with clk125 because it's independent of potentially failing ro_user_clk
    if rising_edge (clk_125) then
       if (ttc_reset_reg(2) = '1') then 
           cpll_lock_lost <= '0';
       elsif (cpll_lock_delay_1 = '0') and (cpll_lock_delay_2 = '1') then --this is falling edge of cplllock
           cpll_lock_lost <= '1';
       else
           cpll_lock_lost <= cpll_lock_lost;
       end if;         
    end if; 
 end process;   
 
TTC_fifo_control_reg: entity work.ipbus_reg_v
  port map( 
     clk => ipb_clk,
     reset => ipb_rst,
     ipbus_in => ipbw(N_SLV_TTC_fifo_control),
     ipbus_out => ipbr(N_SLV_TTC_fifo_control),
     q(0) => ttc_fifo_control
    );
--  0:   busy enable 
--  1:   xoff enable 
--  these bits need to be enable future busy and xoff outputs 
    
 
TTC_reset_register: entity work.ipbus_reg_v
   port map( 
          clk => ipb_clk,
          reset => ttc_rst_rst,
          ipbus_in => ipbw(N_SLV_TTC_reset),
          ipbus_out => ipbr(N_SLV_TTC_reset),
          stb(0) => ttc_rst_stb,
          q(0) => ttc_reset_reg
        );
ttc_rst_rst <= ttc_rst_stb or ipb_rst;
 
ttc_fifo_rst <= ttc_reset_reg(0);
 
TTC_fifo_status_reg: entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TTC_fifo_status),
          ipb_out => ipbr(N_SLV_TTC_fifo_status),
          slv_clk => pp_clock,
          d(0) => TTC_fifo_status,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
TTC_fifo_status(0) <= '1' WHEN (ttc_fifo_level > x"fff") ELSE '0';
TTC_fifo_status(1) <= '1' WHEN (ttc_fifo_level > ttc_fifo_busy_threshold) ELSE  '0';
--TTC_fifo_status(2) <= '1' WHEN (ttc_fifo_level > ttc_fifo_xoff_threshold) ELSE  '0'; 
 
 
 
TTC_fifo_fill_level_reg : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TTC_fifo_fill_level),
          ipb_out => ipbr(N_SLV_TTC_fifo_fill_level),
          slv_clk => pp_clock,
          d(0) => TTC_fifo_fill_level,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
TTC_fifo_fill_level(15 downto 0) <= ttc_fifo_level;
TTC_fifo_fill_level(31 downto 16) <= ttc_watermark;
 
ttc_fifo_watermark : entity work.watermark
   generic map (
         watermark_width => 16
       )
      port map (
            clock => pp_clock,
            level => ttc_fifo_level,
            reset => ttc_watermark_reset,
            watermark => ttc_watermark
        );    
 
ttc_watermark_reset <= (ipb_rst or ttc_reset_reg(1));
 
 
 
 
 
 
TTC_fifo_busy_Count_reg : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TTC_fifo_busy_count),
          ipb_out => ipbr(N_SLV_TTC_fifo_busy_count),
          slv_clk => pp_clock,
          d(0) => TTC_fifo_busy_count,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
 ttc_fifo_busy_counter: entity work.threshold_counter
  port map (
    clock => pp_clock, 
    reset => ttc_reset_reg(2),
    threshold => ttc_fifo_busy_threshold(15 downto 0),
    level  => ttc_fifo_level, 
    above_count => TTC_fifo_busy_Count
    );
 
 
felix_backpressure_reg : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_FELIX_BACKPRESSURE),
          ipb_out => ipbr(N_SLV_FELIX_BACKPRESSURE),
          slv_clk => pp_clock,
          d(0) => (x"00000" & flx_backpressure),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
 
 
 
TTC_fifo_busy_threshold_reg: entity work.ipbus_reg_v   
    port map( 
          clk => ipb_clk,
          reset => ipb_rst,
          ipbus_in => ipbw(N_SLV_TTC_FIFO_BUSY_THRESHOLD),
          ipbus_out => ipbr(N_SLV_TTC_FIFO_BUSY_THRESHOLD),
          q(0) => TTC_FIFO_BUSY_THRESHOLD
        );
 
L1ID_Value_reg : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TTC_L1ID),
          ipb_out => ipbr(N_SLV_TTC_L1ID),
          slv_clk => cttc_user_clk,
          d(0) => ttc_reg(43 downto 12), --(L1ID & ECRID),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
BCN_reg : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TTC_BCN),
          ipb_out => ipbr(N_SLV_TTC_BCN),
          slv_clk => cttc_user_clk,
          d(0) => BCN, 
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
bcn_adjust_reg : entity work.ipbus_reg_v
  port map( 
     clk => ipb_clk,
     reset => ipb_rst,
     ipbus_in => ipbw(N_SLV_BCN_ADJUST),
     ipbus_out => ipbr(N_SLV_BCN_ADJUST),
     q(0) => bcn_adjust_i
    ); 
 
BCN_adjustment <= bcn_adjust_i(11 downto 0);
 
CTTC_link_stat_reg : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_CTTC_link_stat),
          ipb_out => ipbr(N_SLV_CTTC_link_stat),
          slv_clk => cttc_user_clk,
          d(0) => CTTC_link_status,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
 
TTC_control_reg: entity work.ipbus_reg_v
  port map( 
     clk => ipb_clk,
     reset => ipb_rst,
     ipbus_in => ipbw(N_SLV_TTC_control),
     ipbus_out => ipbr(N_SLV_TTC_control),
     q(0) => ttc_control
    );
 
TTC_ignore <= ttc_control(0);
TTC_CRC_ignore <= ttc_control(1);
event_sel(2 downto 0) <= ttc_control(6 downto 4);
 
packet_header_info: entity work.ipbus_reg_v
  port map( 
     clk => ipb_clk,
     reset => ipb_rst,
     ipbus_in => ipbw(N_SLV_Packet_Header_Info),
     ipbus_out => ipbr(N_SLV_Packet_Header_Info),
     q(0) => pkt_hdr_info
    ); 
 
header_sequence  <= pkt_hdr_info(15 downto 4);  
header_type      <= pkt_hdr_info(3 downto 0);
det_spec_evnt_sel<= pkt_hdr_info(19 downto 16); 
 
 
 
 
 
 
total_event_count_reg : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => run_event_count_reset,
          ipb_in => ipbw(N_SLV_total_event_count),
          ipb_out => ipbr(N_SLV_total_event_count),
          slv_clk => cttc_user_clk,
          d(0) => run_event_count(31 downto 0),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
total_event_count_msb : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => run_event_count_reset,
          ipb_in => ipbw(N_SLV_total_event_count_msb),
          ipb_out => ipbr(N_SLV_total_event_count_msb),
          slv_clk => cttc_user_clk,
          d(0) => x"0000000" & run_event_count  (35 downto 32),
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
event_count_reg : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => event_count_reset,
          ipb_in => ipbw(N_SLV_event_count),
          ipb_out => ipbr(N_SLV_event_count),
          slv_clk => cttc_user_clk,
          d(0) => event_count(31 downto 0),
--          d(0) => event_count,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
 
 
 
 
orbit_reg : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => orbit_count_reset,
          ipb_in => ipbw(N_SLV_orbit),
          ipb_out => ipbr(N_SLV_orbit),
          slv_clk => cttc_user_clk,
          d(0) =>  x"0000" & orbit_count  ,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
 
event_count_reset     <= ttc_reset_reg(8) or ipb_rst;
run_event_count_reset <= ttc_reset_reg(9) or ipb_rst;
orbit_count_reset     <= ttc_reset_reg(10) or ipb_rst;
 
-- run total event counter  - not reset by ECR:  provides event count for entire run
 
--process (cttc_user_clk) begin
process (cttc_user_clk, run_event_count_reset) begin
    if (run_event_count_reset = '1') then 
          run_event_count <= X"000000000";
    elsif rising_edge (cttc_user_clk) then
       if (L1A = '1') and (seq = "01") then  
           run_event_count <= (run_event_count + 1);
       else
           run_event_count <= run_event_count;
       end if;
    end if;
end process; 
 
 
--event_count_ila : ttc_regs_ila
--PORT MAP (
--  clk => cttc_user_clk,
--  probe0 => seq, 
--  probe1(0) => L1A, 
--  probe2(0) => event_count_reset, 
--  probe3(0) => '0',
--  probe4 => X"0" & event_count(11 downto 0)
--);
 
 
 
 
 
-- disperity_err_counter: 
 
disperity_err_counter: entity work.error_counter
   generic map (
      cwidth => 8
      )
  port map (
        clock           =>  cttc_user_clk,
        counter_reset   =>  ttc_reset_reg(2),
        system_reset    =>  ipb_rst,
        error           =>  rxdisperr,
        error_count     =>  disp_err_count  
   );    
    
 table_err_counter: entity work.error_counter
      generic map (
         cwidth => 8
         )
     port map (
           clock           =>  cttc_user_clk,
           counter_reset   =>  ttc_reset_reg(2),
           system_reset    =>  ipb_rst,
           error           =>  rxnotintable,
           error_count     =>  table_err_count  
      );       
    
 
 
CTTC_link_status  <= crc_error_count &  disp_err_count & table_err_count & "00" & cpll_lock_lost & cpllrefclklost & cplllock & cpllfbclklost & rxresetdone  & rxfsmresetdone;
 
ttc_reset <= ttc_reset_reg(4);
hub_link_reset <= ttc_reset_reg(5);
 
 crc_err_counter: entity work.error_counter
      generic map (
         cwidth => 8
         )
     port map (
           clock           =>  cttc_user_clk,
           counter_reset   =>  ttc_reset_reg(2),
           system_reset    =>  ipb_rst,
           error           =>  CTTC_CRC_error,
           error_count     =>  crc_error_count  
 
    );
--crc_error_count <= x"00";  --place holder
 
L1id_Continuity_Capture_Control: entity work.ipbus_reg_v
   port map( 
          clk => ipb_clk,
          reset => ccc_rst_rst,
          ipbus_in => ipbw(N_SLV_L1id_Continuity_Capture_Control),
          ipbus_out => ipbr(N_SLV_L1id_Continuity_Capture_Control),
          stb(0) => ccc_rst_stb,
          q(0) => l1id_continuity_control
        );
ccc_rst_rst <= ccc_rst_stb or ipb_rst;
 
 
L1id_Capture_Status_reg: entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_L1ID_CAPTURE_STATUS),
          ipb_out => ipbr(N_SLV_L1ID_CAPTURE_STATUS),
          slv_clk => cttc_user_clk,
          d(0) => l1id_continuity_status,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
Local_Counter_Miss_reg: entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_LOCAL_COUNTER_MISS),
          ipb_out => ipbr(N_SLV_LOCAL_COUNTER_MISS),
          slv_clk => cttc_user_clk,
          d(0) => l1id_local_miss,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
TTC_Miss_reg: entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_TTC_MISS),
          ipb_out => ipbr(N_SLV_TTC_MISS),
          slv_clk => cttc_user_clk,
          d(0) => l1id_ttc_miss,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
Mismatch_err_reg: entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_MISMATCH_ERROR_COUNT),
          ipb_out => ipbr(N_SLV_MISMATCH_ERROR_COUNT),
          slv_clk => cttc_user_clk,
          d(0) => l1id_error_count,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
Timeout_threshold_reg: entity work.ipbus_reg_v   
    port map( 
          clk => ipb_clk,
          reset => ipb_rst,
          ipbus_in => ipbw(N_SLV_TIMEOUT_THRESHOLD),
          ipbus_out => ipbr(N_SLV_TIMEOUT_THRESHOLD),
          q(0) => timeout_threshold
        );
 
Duplicate_L1ID_Count_reg: entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_DUPLICATE_L1ID_COUNT),
          ipb_out => ipbr(N_SLV_DUPLICATE_L1ID_COUNT),
          slv_clk => cttc_user_clk,
          d(0) => repeat_counter,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      );
 
end RTL;