My Project
v0.0.16
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clk125_fr | std_logic |
clk125 | std_logic |
clk_ipb | std_logic |
clk_ipb_i | std_logic |
locked | std_logic |
clk_locked | std_logic |
eth_locked | std_logic |
rst125 | std_logic |
rst_ipb | std_logic |
rst_ipb_ctrl | std_logic |
rst_eth | std_logic |
onehz_i | std_logic |
pkt | std_logic |
mac_tx_data | std_logic_vector ( 7 downto 0 ) |
mac_rx_data | std_logic_vector ( 7 downto 0 ) |
mac_tx_valid | std_logic |
mac_tx_last | std_logic |
mac_tx_error | std_logic |
mac_tx_ready | std_logic |
mac_rx_valid | std_logic |
mac_rx_last | std_logic |
mac_rx_error | std_logic |
led_p | std_logic_vector ( 0 downto 0 ) |
Instantiations | |
clocks | clocks_7s_serdes <Entity clocks_7s_serdes> |
stretch | led_stretcher <Entity led_stretcher> |
eth | eth_7s_1000basex <Entity eth_7s_1000basex> |
ipbus | ipbus_ctrl <Entity ipbus_ctrl> |
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