RTL Architecture Reference

Processes
PROCESS_57	( clk_125 )
PROCESS_58	( clk_125 )
PROCESS_59	( clk_125 )
PROCESS_60	( clk_125 )
PROCESS_61	( channel_up , chan_dis )
PROCESS_62	( pp_clock )
PROCESS_63	( rt_clk , timer_reset , backplane_control( 2 ) )
PROCESS_64	( rt_clk , ipb_rst , busy_active_time_reset )

Components
priority_encoder	<Entity priority_encoder>
clock_test_ipbus	<Entity clock_test_ipbus>

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
time_counter	STD_LOGIC_VECTOR ( 31 downto 0 )
time_count_reg	std_logic_vector ( 31 downto 0 )
backplane_control_reg_rst	std_logic
backplane_control_reg_stb	std_logic
first_chan_i	STD_LOGIC_vector ( 4 downto 0 )
last_chan_i	STD_LOGIC_vector ( 4 downto 0 )
first_last	STD_LOGIC_vector ( 31 downto 0 )
chan_ena	STD_LOGIC_vector ( 23 downto 0 )
chan_dis	STD_LOGIC_vector ( 31 downto 0 )
ro_status_32	STD_LOGIC_vector ( 31 downto 0 )
count_40	STD_LOGIC_vector ( 7 downto 0 )
count_160	STD_LOGIC_vector ( 7 downto 0 )
count_125	STD_LOGIC_vector ( 7 downto 0 )
clk_40_good	STD_LOGIC
clk_160_good	STD_LOGIC
clock_status_32	STD_LOGIC_vector ( 31 downto 0 )
backplane_control_two	STD_LOGIC_vector ( 31 downto 0 )
backplane_control_i	STD_LOGIC_vector ( 31 downto 0 )
clk_test_reset	STD_LOGIC
SMBALERT	STD_LOGIC
T_WARN	STD_LOGIC
busy_active_time	STD_LOGIC_vector ( 31 downto 0 )
busy_active_time_reset	STD_LOGIC
ro_cpll_lock	STD_LOGIC
ro_cpll_lock_delay_1	STD_LOGIC
ro_cpll_lock_delay_2	STD_LOGIC
ro_cpll_lock_lost	STD_LOGIC
CK_INT_delay_1	STD_LOGIC
CK_INT_delay_2	STD_LOGIC
silab_ck_int_sticky	STD_LOGIC
chan_enable_r1	STD_LOGIC_vector ( 23 downto 0 )
chan_enable_r2	STD_LOGIC_vector ( 23 downto 0 )

Attributes
ASYNC_REG	string
ASYNC_REG	signal is " TRUE "

Instantiations
fabric	ipbus_fabric_sel
time_count_value	ipbus_syncreg_v
tob_fifo_busy_threshold_reg	ipbus_reg_v
tob_fifo_xoff_threshold_reg	ipbus_reg_v
bulk_fifo_busy_threshold_reg	ipbus_reg_v
bulk_fifo_xoff_threshold_reg	ipbus_reg_v
backplane_control_reg	ipbus_reg_v
backplane_control_reg_2_reg	ipbus_reg_v
channel_map	ipbus_syncreg_v
channel_disable	ipbus_reg_v
first_last_chan	ipbus_syncreg_v
ro_ctrl_status	ipbus_syncreg_v
clock_status	ipbus_syncreg_v
first_last_encode	priority_encoder <Entity priority_encoder>
clk_tester	clock_test_ipbus <Entity clock_test_ipbus>
busy_active_time_reg	ipbus_syncreg_v

Detailed Description

Definition at line 78 of file backplane_regs.vhd.

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The documentation for this class was generated from the following file:

• ROD/packet_processor/hdl/backplane_regs.vhd