backplane_regs.vhd

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 24.04.2019 10:41:24
-- Design Name: 
-- Module Name: backplane_regs - RTL
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
--use work.ipbus_decode_jfex_chan_regs.all;
--use work.ipbus_decode_rod_backplane_regs.all;
use work.ipbus_decode_L1CaloHubRodBackplaneRegisters.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity backplane_regs is
    Port ( 
     ipb_clk: in std_logic;
     ipb_rst: in std_logic;
     ipb_in: in ipb_wbus;
     ipb_out: out ipb_rbus;
     
     pp_clock        : in std_logic;   
     clk_40          : in std_logic;
     clk_160         : in std_logic;
     clk_125         : in std_logic;
     rt_clk          : in std_logic;
     ck_pll_lock     : in std_logic; 
     timer_reset     : in std_logic;   
--     proc_soft_reset : out std_logic;
     
     CK_INT           : in STD_LOGIC;
     SMBALERT_B       : in STD_LOGIC;
     T_WRN_B          : in STD_LOGIC;
 
 
     channel_up      : in STD_LOGIC_VECTOR (23 downto 0);
     chan_enable     : out STD_LOGIC_VECTOR (23 downto 0);
     first_chan      : out STD_LOGIC_vector(4 downto 0);
     last_chan       : out STD_LOGIC_vector(4 downto 0);
     ro_status       : in STD_LOGIC_VECTOR (7 downto 0);
     
     time_count      : out STD_LOGIC_VECTOR (31 downto 0);   --synchronous to the pp_clock        
     tob_fifo_busy_threshold : out STD_LOGIC_VECTOR (31 downto 0); --synchronous to ipb_clk
     bulk_fifo_busy_threshold : out STD_LOGIC_VECTOR (31 downto 0); --synchronous to ipb_clk
     tob_fifo_xoff_threshold : out STD_LOGIC_VECTOR (31 downto 0); --synchronous to ipb_clk
     bulk_fifo_xoff_threshold : out STD_LOGIC_VECTOR (31 downto 0); --synchronous to ipb_clk
     backplane_control : out STD_LOGIC_VECTOR (31 downto 0);
--     backplane_ttc_control : out STD_LOGIC_VECTOR (31 downto 0);
     chan_disable           : out STD_LOGIC_VECTOR (31 downto 0);
     combined_busy           : in  std_logic;
     ro_user_clock           : in  std_logic      
     );
end backplane_regs;
architecture RTL of backplane_regs is
 
component priority_encoder 
    Port ( 
           chan_ena : in STD_LOGIC_VECTOR (23 downto 0);
           clock : in STD_LOGIC;
           first_chan : out STD_LOGIC_vector(4 downto 0);
           last_chan : out STD_LOGIC_vector(4 downto 0)
           );
end component;
 
component clock_test_ipbus is
  generic
(
 COUNTER_WIDTH_40  : integer :=   8;
 reset_count       : std_logic_vector(15 downto 0) := x"03ff";   --count_125 rollover resets the system
 count_40_term     : std_logic_vector(7 downto 0) := x"45";    
 count_160_term    : std_logic_vector(7 downto 0) := x"45"  
 
 --for a shorter test sequence, use the values below 
 --reset_count       : std_logic_vector(15 downto 0) := x"01ff";   --count_125 rollover resets the system
 --count_40_term     : std_logic_vector(7 downto 0) := x"A2";    
 --count_160_term    : std_logic_vector(7 downto 0) := x"A2"  
);    
 
    Port ( 
               clock_40         : in STD_LOGIC;
               clock_160        : in STD_LOGIC;
               clock_125        : in STD_LOGIC;
               reset            : in STD_LOGIC;
               clock_160_lock   : in STD_LOGIC;
               clk_40_good      : out std_logic;
               clk_160_good     : out std_logic;
               count_40         : out std_logic_vector(counter_width_40-1 downto 0);
               count_160        : out std_logic_vector(counter_width_40-1 downto 0);
               count_125        : out std_logic_vector(counter_width_40-1 downto 0)
                
               );
end component;
 
 
 
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal time_counter :  STD_LOGIC_VECTOR (31 downto 0);
signal time_count_reg :  std_logic_vector( 31 downto 0);
 
signal  backplane_control_reg_rst : std_logic;
signal  backplane_control_reg_stb : std_logic;
 
signal first_chan_i :  STD_LOGIC_vector(4 downto 0);
signal last_chan_i  :  STD_LOGIC_vector(4 downto 0);
signal first_last   :  STD_LOGIC_vector(31 downto 0);
 
signal chan_ena     :  STD_LOGIC_vector(23 downto 0);
signal chan_dis     :  STD_LOGIC_vector(31 downto 0);
signal ro_status_32 :  STD_LOGIC_vector(31 downto 0);
 
signal count_40     :  STD_LOGIC_vector(7 downto 0);
signal count_160    :  STD_LOGIC_vector(7 downto 0);
signal count_125    :  STD_LOGIC_vector(7 downto 0);
signal clk_40_good  :  STD_LOGIC;
signal clk_160_good  :  STD_LOGIC;
 
signal clock_status_32 : STD_LOGIC_vector(31 downto 0);
 
signal backplane_control_two : STD_LOGIC_vector(31 downto 0);
signal backplane_control_i : STD_LOGIC_vector(31 downto 0);
 
signal clk_test_reset :  STD_LOGIC;
 
signal  SMBALERT     : STD_LOGIC;
signal  T_WARN       : STD_LOGIC;
 
signal  busy_active_time       : STD_LOGIC_vector(31 downto 0);
signal  busy_active_time_reset : STD_LOGIC;
 
signal  ro_cpll_lock           : STD_LOGIC;
signal  ro_cpll_lock_delay_1   : STD_LOGIC;
signal  ro_cpll_lock_delay_2   : STD_LOGIC;
signal  ro_cpll_lock_lost      : STD_LOGIC;
 
signal  CK_INT_delay_1         : STD_LOGIC;
signal  CK_INT_delay_2         : STD_LOGIC;
signal  silab_ck_int_sticky    : STD_LOGIC;
 
 
attribute ASYNC_REG                        : string;
signal  chan_enable_r1         : STD_LOGIC_vector(23 downto 0);
attribute ASYNC_REG of chan_enable_r1  : signal is "TRUE";
signal  chan_enable_r2         : STD_LOGIC_vector(23 downto 0);
attribute ASYNC_REG of chan_enable_r2  : signal is "TRUE";
 
begin
 
-- ipbus address decode
 
fabric: entity work.ipbus_fabric_sel
  generic map(
    NSLV => N_SLAVES,
    SEL_WIDTH => IPBUS_SEL_WIDTH)
  port map(
   ipb_in => ipb_in,
   ipb_out => ipb_out,
--      sel => ipbus_decode_my_module(ipb_in.ipb_addr),
--      sel => ipbus_sel_my_module(ipb_in.ipb_addr),
--      sel => ipbus_sel_jfex_chan_regs(ipb_in.ipb_addr),
--    sel => ipbus_sel_rod_backplane_regs(ipb_in.ipb_addr),
    sel => ipbus_sel_L1CaloHubRodBackplaneRegisters(ipb_in.ipb_addr),
    ipb_to_slaves => ipbw,
    ipb_from_slaves => ipbr
  );
 
 
 
 
--addr 0
Time_count_value: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
--          ipb_in => ipbw(N_SLV_BACKPLANE_TIME_COUNT_VALUE),
--          ipb_out => ipbr(N_SLV_BACKPLANE_TIME_COUNT_VALUE),
          ipb_in => ipbw(N_SLV_TIME_COUNT_VALUE),
          ipb_out => ipbr(N_SLV_TIME_COUNT_VALUE),
          slv_clk => rt_clk,
          d(0) => time_count_reg,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
 
--addr 1
Tob_fifo_busy_threshold_reg: entity work.ipbus_reg_v   
    port map( 
          clk => ipb_clk,
          reset => ipb_rst,
--          ipbus_in => ipbw(N_SLV_BACKPLANE_TOB_FIFO_BUSY_THRESHOLD),
--          ipbus_out => ipbr(N_SLV_BACKPLANE_TOB_FIFO_BUSY_THRESHOLD),
          ipbus_in => ipbw(N_SLV_TOB_FIFO_BUSY_THRESHOLD),
          ipbus_out => ipbr(N_SLV_TOB_FIFO_BUSY_THRESHOLD),
          q(0) => TOB_FIFO_BUSY_THRESHOLD
        );
 
--addr 2
Tob_fifo_xoff_threshold_reg: entity work.ipbus_reg_v
    port map( 
          clk => ipb_clk,
          reset => ipb_rst,
--          ipbus_in => ipbw(N_SLV_BACKPLANE_TOB_FIFO_XOFF_THRESHOLD),
--          ipbus_out => ipbr(N_SLV_BACKPLANE_TOB_FIFO_XOFF_THRESHOLD),
          ipbus_in => ipbw(N_SLV_TOB_FIFO_XOFF_THRESHOLD),
          ipbus_out => ipbr(N_SLV_TOB_FIFO_XOFF_THRESHOLD),
          q(0) => tob_fifo_xoff_threshold
        );
 
 
--addr 3
Bulk_fifo_busy_threshold_reg: entity work.ipbus_reg_v
    port map( 
          clk => ipb_clk,
          reset => ipb_rst,
--          ipbus_in => ipbw(N_SLV_BACKPLANE_BULK_FIFO_BUSY_THRESHOLD),
--          ipbus_out => ipbr(N_SLV_BACKPLANE_BULK_FIFO_BUSY_THRESHOLD),
          ipbus_in => ipbw(N_SLV_BULK_FIFO_BUSY_THRESHOLD),
          ipbus_out => ipbr(N_SLV_BULK_FIFO_BUSY_THRESHOLD),
          q(0) => bulk_fifo_busy_threshold
        );
 
 
 
--addr 4
Bulk_fifo_xoff_threshold_reg: entity work.ipbus_reg_v
    port map( 
          clk => ipb_clk,
          reset => ipb_rst,
--          ipbus_in => ipbw(N_SLV_BACKPLANE_BULK_FIFO_XOFF_THRESHOLD),
--          ipbus_out => ipbr(N_SLV_BACKPLANE_BULK_FIFO_XOFF_THRESHOLD),
          ipbus_in => ipbw(N_SLV_BULK_FIFO_XOFF_THRESHOLD),
          ipbus_out => ipbr(N_SLV_BULK_FIFO_XOFF_THRESHOLD),
          q(0) => bulk_fifo_xoff_threshold
        );
 
--addr 5
--Backplane_control_reg: entity work.ipbus_reg_v
--    port map( 
--          clk => ipb_clk,
--          reset => ipb_rst,
--          ipbus_in => ipbw(N_SLV_BACKPLANE_BACKPLANE_CONTROL),
--          ipbus_out => ipbr(N_SLV_BACKPLANE_BACKPLANE_CONTROL),
--          q(0) => backplane_control
--        );
 
--addr 5
 
backplane_control_reg: entity work.ipbus_reg_v
   port map( 
          clk => ipb_clk,
          reset => backplane_control_reg_rst,
--          ipbus_in => ipbw(N_SLV_BACKPLANE_BACKPLANE_CONTROL),
--          ipbus_out => ipbr(N_SLV_BACKPLANE_BACKPLANE_CONTROL),
          ipbus_in => ipbw(N_SLV_BACKPLANE_CONTROL),
          ipbus_out => ipbr(N_SLV_BACKPLANE_CONTROL),
          stb(0) => backplane_control_reg_stb,
          q(0) => backplane_control_i
        );
backplane_control_reg_rst <=  backplane_control_reg_stb or ipb_rst;
backplane_control(28 downto 0) <= backplane_control_i(28 downto 0);  --29, 30 and 31 are used by reg_2
 
Backplane_control_reg_2_reg: entity work.ipbus_reg_v
    port map( 
          clk => ipb_clk,
          reset => ipb_rst,
          ipbus_in => ipbw(N_SLV_BACKPLANE_CONTROL_2),
          ipbus_out => ipbr(N_SLV_BACKPLANE_CONTROL_2),
          q(0) => backplane_control_two
        );
 
backplane_control(31) <= backplane_control_two(0);
--backplane_control(30) <= not backplane_control_two(1);  --LPM mode by default - set for dfe mode
backplane_control(30) <= '1'; --Aurora LPM enable 
backplane_control(29) <= backplane_control_two(1);
 
 
--backplane_TTC_control_reg: entity work.ipbus_reg_v
--   port map( 
--          clk => ipb_clk,
--          reset =>  ipb_rst,
----          ipbus_in => ipbw(N_SLV_BACKPLANE_TTC_CONTROL),
----          ipbus_out => ipbr(N_SLV_BACKPLANE_TTC_CONTROL),
--          ipbus_in => ipbw(N_SLV_TTC_CONTROL),
--          ipbus_out => ipbr(N_SLV_TTC_CONTROL),          
----          stb(0) => backplane_TTC_control_reg_stb,
--          q(0) => backplane_ttc_control
--        );
 
channel_map: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
--          ipb_in => ipbw(N_SLV_BACKPLANE_CHANNEL_MAP),
--          ipb_out => ipbr(N_SLV_BACKPLANE_CHANNEL_MAP),
          ipb_in => ipbw(N_SLV_CHANNEL_MAP),
          ipb_out => ipbr(N_SLV_CHANNEL_MAP),          
          slv_clk => pp_clock,
          d(0) => x"00" & chan_ena  ,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
 
channel_disable: entity work.ipbus_reg_v
   port map( 
          clk => ipb_clk,
          reset =>  ipb_rst,
--          ipbus_in =>  ipbw(N_SLV_BACKPLANE_CHAN_DISABLE),
--          ipbus_out => ipbr(N_SLV_BACKPLANE_CHAN_DISABLE),
          ipbus_in =>  ipbw(N_SLV_CHAN_DISABLE),
          ipbus_out => ipbr(N_SLV_CHAN_DISABLE),          
--          stb(0) => backplane_TTC_control_reg_stb,
          q(0) => chan_dis
        );
 
chan_disable <= chan_dis;
 
 
first_last_chan: entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
--          ipb_in => ipbw(N_SLV_BACKPLANE_FIRST_LAST_CHAN),
--          ipb_out => ipbr(N_SLV_BACKPLANE_FIRST_LAST_CHAN),
          ipb_in => ipbw(N_SLV_FIRST_LAST_CHAN),
          ipb_out => ipbr(N_SLV_FIRST_LAST_CHAN),          
          slv_clk => pp_clock,
          d(0) => first_last,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
--address 6
ro_ctrl_status : entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
--          ipb_in => ipbw(N_SLV_BACKPLANE_RO_CTRL_LINK_STAT),
--          ipb_out => ipbr(N_SLV_BACKPLANE_RO_CTRL_LINK_STAT),
          ipb_in => ipbw(N_SLV_RO_CTRL_LINK_STAT),
          ipb_out => ipbr(N_SLV_RO_CTRL_LINK_STAT),          
          slv_clk => pp_clock,
          d(0) => ro_status_32,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
--ro_status_32 <= (x"000000" & ro_status);
ro_status_32 <= (x"000000" & "00" & ro_cpll_lock_lost & ro_status(4 downto 0));
 
--readout control cpll lock lost sticky bit --------
 
ro_cpll_lock <= ro_status(3);
 
process (clk_125) begin         --sample with clk125 because it's independent of potentially failing ro_user_clk
    if rising_edge (clk_125) then
       ro_cpll_lock_delay_1 <= ro_cpll_lock;
       ro_cpll_lock_delay_2 <= ro_cpll_lock_delay_1;
    end if;
end process;      
 
 
process (clk_125) begin      --sample with clk125 because it's independent of potentially failing ro_user_clk
    if rising_edge (clk_125) then
       if (backplane_control(3) = '1') then 
           ro_cpll_lock_lost <= '0';
       elsif (ro_cpll_lock_delay_1 = '0') and (ro_cpll_lock_delay_2 = '1') then --this is falling edge of cplllock
           ro_cpll_lock_lost <= '1';
       else
           ro_cpll_lock_lost <= ro_cpll_lock_lost;
       end if;         
    end if; 
 end process;   
 
 
 
 
clock_status : entity work.ipbus_syncreg_v
    generic map (
       N_CTRL => 0,
       N_STAT => 1
     )
    port map( 
          clk => ipb_clk,
          rst => ipb_rst,
--          ipb_in => ipbw(N_SLV_BACKPLANE_RO_CTRL_LINK_STAT),
--          ipb_out => ipbr(N_SLV_BACKPLANE_RO_CTRL_LINK_STAT),
          ipb_in => ipbw(N_SLV_CLOCK_STATUS),
          ipb_out => ipbr(N_SLV_CLOCK_STATUS),          
          slv_clk => pp_clock,
          d(0) =>  clock_status_32,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open  
        );
 
 
clock_status_32(31 downto 24)  <= count_125;
clock_status_32(23 downto 16)  <= count_40;
clock_status_32(15 downto 8)   <= count_160;
 
clock_status_32(6) <= silab_ck_int_sticky;
clock_status_32(5) <= SMBALERT;
clock_status_32(4) <= T_WARN;
clock_status_32(3) <= CK_INT;
clock_status_32(2) <= clk_40_good;
clock_status_32(1) <= clk_160_good;
clock_status_32(0) <= ck_pll_lock;
 
T_WARN <= not T_WRN_B;
SMBALERT <= not SMBALERT_B;
 
 
process (clk_125) begin
    if rising_edge (clk_125) then
       CK_INT_delay_1 <= CK_INT;
       CK_INT_delay_2 <= CK_INT_delay_1;
    end if;
end process;    
 
process (clk_125) begin
    if rising_edge (clk_125) then
       if (backplane_control(9) = '1') then 
           silab_ck_int_sticky <= '0';
       elsif (CK_INT_delay_1 = '0') and (CK_INT_delay_2 = '1') then --this is falling edge of cplllock
           silab_ck_int_sticky <= '1';
       else
           silab_ck_int_sticky <= silab_ck_int_sticky;
       end if;         
    end if; 
 end process;
 
 
 
 
--process(channel_up)
process(channel_up, chan_dis)
   begin       
      for i in 23 downto 0 loop
             chan_ena(i) <= channel_up(i) AND NOT chan_dis(i);                  
         end loop;
  end process;
        
--chan_enable <=  chan_ena;       
 
process (pp_clock) begin
    if rising_edge (pp_clock) then
       chan_enable_r1 <= chan_ena;
       chan_enable_r2 <= chan_enable_r1;
    end if; 
 end process;
 
chan_enable <=  chan_enable_r2;
--place holder---------------------------------------------------------------------
------------add TTC and Readout Control MGT status and control in here --------------
---------------------------------------------------------------------------------
--but, actually, TTC fifo should look similar to one of the channels, so perhaps it should have its own reg bank like the aurora channels
--------------------------------------------------------------------------------------------------------------------------------------------
 
--place holder 
-- add clock tester and register here 
--     need to import clk40 
 
 
 
 
 
 
--process(rt_clk, timer_reset)
process(rt_clk, timer_reset, backplane_control(2))
    begin
        if (timer_reset = '1') or (backplane_control(2) = '1')  then                     -- async (p)reset -> put 'reset in sensitivity list
            time_counter <= (others => '0');
        elsif rising_edge(rt_clk) then 
              time_counter <= (time_counter + 1); 
        end if; 
 end process;
 
 
time_count <= time_counter(31 downto 0);
time_count_reg <= time_counter(31 downto 0);
 
first_last_encode :  priority_encoder 
    Port map ( 
           chan_ena    => chan_ena,
           clock        => pp_clock,
           first_chan   => first_chan_i,
           last_chan    => last_chan_i
           );
 
first_chan <= first_chan_i;
last_chan  <= last_chan_i;
first_last <= x"00" & "000" & last_chan_i & x"00" & "000" & first_chan_i;
 
 
 
 
 
clk_tester : clock_test_ipbus 
   generic map ( 
       reset_count => x"03ff",
       count_40_term => x"45",
       count_160_term => x"45"     
 --       reset_count => x"01ff",
 --      count_40_term => x"a2",
 --      count_160_term => x"a2"
       )
   port map (
       clock_40  => clk_40, 
       clock_160 => clk_160, 
       clock_125 => clk_125, 
       reset     => clk_test_reset,
       clock_160_lock => ck_pll_lock,
       clk_40_good    => clk_40_good,
       clk_160_good   => clk_160_good,
       count_40 => count_40,
       count_160  => count_160,
       count_125 => count_125
 );
 
clk_test_reset <= backplane_control(7) ;
 
 
busy_active_time_reg : entity work.ipbus_syncreg_v 
   generic map (
          N_CTRL => 0,
          N_STAT => 1
        )
       port map (
          clk => ipb_clk,
          rst => ipb_rst,
          ipb_in => ipbw(N_SLV_Busy_Active_TIME),
          ipb_out => ipbr(N_SLV_Busy_Active_TIME),
          slv_clk => rt_clk, --pp_clock,
          d(0) => busy_active_time,
          qmask => (others => (others => '1')),
          stb => open,
          rstb => open           
      ); 
 
busy_active_time_reset <= backplane_control_i(8);
 
 
process(rt_clk, ipb_rst, busy_active_time_reset)
    begin
        if (ipb_rst or busy_active_time_reset) = '1' then                     -- async (p)reset -> put 'reset in sensitivity list
            busy_active_time <= (others => '0');
        elsif rising_edge(rt_clk) then
            if (combined_busy = '1') and (busy_active_time < x"ffffffff")  then 
              busy_active_time <= (busy_active_time + 1);
            else 
              busy_active_time <= busy_active_time; 
            end if; 
        end if; 
 end process;
 
 
 
 
end RTL;