My Project
v0.0.16
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Signals | |
clk125_fr | std_logic |
clk125 | std_logic |
clk200 | std_logic |
ipb_clk | std_logic |
clk_locked | std_logic |
locked | std_logic |
eth_locked | std_logic |
rsti_125 | std_logic |
rsti_ipb | std_logic |
rsti_eth | std_logic |
rsti_ipb_ctrl | std_logic |
onehz | std_logic |
rsti_fr | std_logic |
mac_tx_data | std_logic_vector ( 7 downto 0 ) |
mac_rx_data | std_logic_vector ( 7 downto 0 ) |
mac_tx_valid | std_logic |
mac_tx_last | std_logic |
mac_tx_error | std_logic |
mac_tx_ready | std_logic |
mac_rx_valid | std_logic |
mac_rx_last | std_logic |
mac_rx_error | std_logic |
pkt | std_logic |
pkt_oob | std_logic |
ipb_out_m | ipb_wbus |
ipb_in_m | ipb_rbus |
oob_in | ipbus_trans_in |
oob_out | ipbus_trans_out |
uc_wdata | std_logic_vector ( 15 downto 0 ) |
test_wdata | std_logic_vector ( 15 downto 0 ) |
uc_rdata | std_logic_vector ( 15 downto 0 ) |
test_rdata | std_logic_vector ( 15 downto 0 ) |
mmc_wdata | std_logic_vector ( 15 downto 0 ) |
mmc_rdata | std_logic_vector ( 15 downto 0 ) |
uc_we | std_logic |
test_we | std_logic |
uc_re | std_logic |
test_re | std_logic |
mmc_we | std_logic |
mmc_re | std_logic |
uc_req | std_logic |
test_req | std_logic |
uc_bdone | std_logic |
test_bdone | std_logic |
mmc_req | std_logic |
mmc_done | std_logic |
ipbw | ipb_wbus_array ( N_SLAVES- 1 downto 0 ) |
ipbr | ipb_rbus_array ( N_SLAVES- 1 downto 0 ) |
led_q | std_logic_vector ( 3 downto 0 ) |
Attributes | |
KEEP | string |
KEEP | clk125_fr : signal is " TRUE " |
Instantiations | |
clocks | clocks_7s_serdes <Entity clocks_7s_serdes> |
stretch | led_stretcher <Entity led_stretcher> |
eth | eth_7s_1000basex <Entity eth_7s_1000basex> |
ipbus | ipbus_ctrl <Entity ipbus_ctrl> |
fabric | ipbus_fabric_sel <Entity ipbus_fabric_sel> |
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