Processes
PROCESS_115	( clock )
PROCESS_116	( clock , reset , current_state , flx_backpressure , flx_bp_enable , header_fifo_valid , chan_enable , current_chan , num_chan , any_chan_read , timeout_1 , timeout_n , s_tvalid , tob_pkt_active , lead_follow_b_reg , chan_in , s_header_mark , s_hdr_crc_tag , comb_error , L1ID_reg_eq , TTC_ignore , L1ID_eq , empty_pkt_active , s_trailer_mark , next_chan , chan_enable_del , chan_crc20_err , chan_len_error , last_chan_read , bad_l1id_flag , first_chan )
PROCESS_117	( clock )
	catch all in case of reset or unknown state
PROCESS_118	( clock )
	–add reset conditions
PROCESS_119	( clock )
PROCESS_120	( clock )
PROCESS_121	( clock )
PROCESS_122	( clock )
PROCESS_123	( clock )
PROCESS_124	( clock )
PROCESS_125	( clock )
PROCESS_126	( clock )
PROCESS_127	( clock )
PROCESS_128	( clock )
PROCESS_129	( clock )
PROCESS_130	( clock )
PROCESS_131	( clock )
PROCESS_132	( clock )
PROCESS_133	( clock )
PROCESS_134	( clock )
PROCESS_135	( clock )
PROCESS_136	( clock )
PROCESS_137	( clock )
PROCESS_138	( clock )
PROCESS_139	( clock )
PROCESS_140	( clock )
PROCESS_141	( clock )
PROCESS_142	( clock )
PROCESS_143	( clock )
PROCESS_144	( clock )
PROCESS_145	( clock )
PROCESS_146	( event_sel( 0 ) , rod_slot )
PROCESS_147	( clock )
PROCESS_148	( clock )
PROCESS_149	( clock )
PROCESS_150	( clock )
PROCESS_151	( clock )
PROCESS_152	( clock )
PROCESS_153	( clock )
PROCESS_154	( clock )
PROCESS_155	( clock )

Signals
s_axis_aresetn	std_logic
tob_data_count	STD_LOGIC_VECTOR ( 31 downto 0 )
tob_wr_data_count	STD_LOGIC_VECTOR ( 31 downto 0 )
tob_rd_data_count	STD_LOGIC_VECTOR ( 31 downto 0 )
hp_empty	std_logic
no_other_match	std_logic
hdr_reg_valid	std_logic := ' 0 '
header_reg	STD_LOGIC_VECTOR ( ( bp_width- 1 ) downto 0 )
header_reg_ex	STD_LOGIC_VECTOR ( ( header_width- bp_width ) downto 0 )
empty_out	std_logic := ' 1 '
poll	std_logic := ' 0 '
inc_chan	std_logic := ' 0 '
match_out	std_logic := ' 0 '
read_active	std_logic := ' 0 '
load_last_chan	std_logic
load_hdr_reg	std_logic
fifo_s_tvalid	std_logic
fifo_s_tlast	std_logic
current_state	state_type
next_state	state_type
next1	state_type
ctrl_code	controls_type
chan_len_cnt	STD_LOGIC_VECTOR ( 11 downto 0 ) := " 000000000000 "
corrected_length	STD_LOGIC_VECTOR ( 15 downto 0 ) := x " 0000 "
pkt_len_cnt	STD_LOGIC_VECTOR ( 15 downto 0 ) := x " 0000 "
pkt_len_cnt_dly	STD_LOGIC_VECTOR ( 15 downto 0 ) := x " 0000 "
fifo_s_tready	std_logic
hdr_fifo_wr	std_logic
rod_header	STD_LOGIC_VECTOR ( 63 downto 0 )
lead_follow_b_reg	std_logic
sel_packet_header	std_logic
sel_packet_header_2	std_logic
sel_packet_trailer	std_logic
chan_len_error	std_logic := ' 0 '
dbg_chan_len_error	std_logic := ' 0 '
trailer_crc20_calc	std_logic
trailer_crc20_reset	std_logic
chan_trailer_crc20_calc	std_logic
chan_trailer_crc20_reset	std_logic
proposed_crc20	STD_LOGIC_VECTOR ( 19 downto 0 )
hdr_out_crc9_start	std_logic
hdr_out_crc9_valid	std_logic
trailer_crc20	STD_LOGIC_VECTOR ( 19 downto 0 )
chan_crc20_err	std_logic
timeout_error	std_logic
dbg_timeout_error	std_logic
chan_trailer_crc20	STD_LOGIC_VECTOR ( 19 downto 0 )
fifo_s_tdata	STD_LOGIC_VECTOR ( bp_width- 1 downto 0 )
evnt_sel	STD_LOGIC_VECTOR ( 3 downto 0 )
next_chan	STD_LOGIC_VECTOR ( 4 downto 0 )
L1ID_eq	std_logic
L1ID_reg_eq	std_logic
L1ID_reg_lt	std_logic
L1ID_reg_gt	std_logic
L1ID_eq_pipe	std_logic
BCN	STD_LOGIC_VECTOR ( 11 downto 0 )
BCID_reg	STD_LOGIC_VECTOR ( 11 downto 0 )
L1ID	STD_LOGIC_VECTOR ( 23 downto 0 )
ECRID	STD_LOGIC_VECTOR ( 7 downto 0 )
orbit	STD_LOGIC_VECTOR ( 15 downto 0 )
header_reg_0	STD_LOGIC_VECTOR ( 31 downto 0 )
header_reg_1	STD_LOGIC_VECTOR ( 31 downto 0 )
header_reg_2	STD_LOGIC_VECTOR ( 31 downto 0 )
version	STD_LOGIC_VECTOR ( 2 downto 0 )
pkt_type	STD_LOGIC_VECTOR ( 3 downto 0 )
header_crc	STD_LOGIC_VECTOR ( 8 downto 0 )
h_sequence	STD_LOGIC_VECTOR ( 11 downto 0 )
tob_stream_id	STD_LOGIC_VECTOR ( 7 downto 0 )
chan_hdr_crc_err	std_logic
header_crc_start	std_logic
rod_number	STD_LOGIC_VECTOR ( 1 downto 0 )
rod_link_error_map	STD_LOGIC_VECTOR ( 11 downto 0 )
rod_error_map	STD_LOGIC_VECTOR ( 6 downto 0 )
dbg_link_error_map	STD_LOGIC_VECTOR ( 11 downto 0 )
dbg_error_map	STD_LOGIC_VECTOR ( 6 downto 0 )
corr_trail_chan	STD_LOGIC_VECTOR ( 4 downto 0 ) := " 00000 "
LMEM	STD_LOGIC_VECTOR ( 3 downto 0 )
dbg_LMEM	STD_LOGIC_VECTOR ( 3 downto 0 )
event_trailer	STD_LOGIC_VECTOR ( 63 downto 0 )
corr_trailer	STD_LOGIC_VECTOR ( 63 downto 0 )
L1ID_ttc_hreg	STD_LOGIC_VECTOR ( 23 downto 0 )
L1id_ttc_32_reg	STD_LOGIC_VECTOR ( 31 downto 0 )
ECRID_ttc_hreg	STD_LOGIC_VECTOR ( 7 downto 0 )
S_tdata_swap	STD_LOGIC_VECTOR ( 63 downto 0 )
m_tdata_i	STD_LOGIC_VECTOR ( 63 downto 0 )
m_tvalid_i	STD_LOGIC
m_tlast_i	STD_LOGIC
m_header_marker_i	STD_LOGIC
m_tail_marker_i	STD_LOGIC
state	state_type
tob_m_tvalid_i	STD_LOGIC
tob_m_tlast_i	STD_LOGIC
tob_m_tready	STD_LOGIC
tob_m_header_marker_i	STD_LOGIC
tob_m_tail_marker_i	STD_LOGIC
tob_m_tdata_i	STD_LOGIC_VECTOR ( 63 downto 0 )
s_tlast_del	STD_LOGIC
s_tlast_del2	STD_LOGIC
dbg_s_tvalid	STD_LOGIC
dbg_s_tlast	STD_LOGIC
dbg_s_tready	STD_LOGIC
dbg_s_tdata	STD_LOGIC_VECTOR ( 63 downto 0 )
dbg_header_reg	STD_LOGIC_VECTOR ( 63 downto 0 )
dbg_header_reg_tmp	STD_LOGIC_VECTOR ( 63 downto 0 )
dbg_corr_trailer	STD_LOGIC_VECTOR ( 63 downto 0 )
dbg_stream_id	STD_LOGIC_VECTOR ( 7 downto 0 )
dbg_m_tvalid_i	STD_LOGIC
dbg_m_tlast_i	STD_LOGIC
dbg_m_tready	STD_LOGIC
dbg_m_header_marker_i	STD_LOGIC
dbg_m_tail_marker_i	STD_LOGIC
dbg_m_tdata_i	STD_LOGIC_VECTOR ( 63 downto 0 )
dbg_crc9_in_flip	STD_LOGIC_VECTOR ( 63 downto 0 )
dbg_hdr_CRC	STD_LOGIC_VECTOR ( 8 downto 0 )
dbg_crc9_calc	STD_LOGIC
dgb_crc9_reset	STD_LOGIC
hdr_in_crc9_reset	STD_LOGIC
dbg_sel	STD_LOGIC_VECTOR ( 1 downto 0 )
sel_dbg_header	STD_LOGIC
sel_dbg_trailer	STD_LOGIC
sel_corr_trailer	STD_LOGIC
dbg_trailer_CRC	STD_LOGIC_VECTOR ( 19 downto 0 )
dbg_crc20_calc	STD_LOGIC
dbg_crc20_in_flip	STD_LOGIC_VECTOR ( 63 downto 0 )
dgb_crc20_reset	STD_LOGIC
dbg_LenCount_Ena	STD_LOGIC
dbg_LenCount_Rst	STD_LOGIC
dbg_LenCount	STD_LOGIC_VECTOR ( 14 downto 0 )
dbg_chan_LenCount	STD_LOGIC_VECTOR ( 11 downto 0 )
dbg_pkt_count_i	STD_LOGIC_VECTOR ( 31 downto 0 )
tobsel	STD_LOGIC
corr_trailer_len_flag	STD_LOGIC
corr_trailer_pe_flag	STD_LOGIC
chan_crc_dmux_ctrl	STD_LOGIC
chan_crc_dmux_data	STD_LOGIC_VECTOR ( 63 downto 0 )
chan_crc_din	STD_LOGIC_VECTOR ( 63 downto 0 )
m_tdata_buf	STD_LOGIC_VECTOR ( 63 downto 0 )
m_tvalid_buf	STD_LOGIC
m_tlast_buf	STD_LOGIC
m_header_marker_buf	STD_LOGIC
m_tail_marker_buf	STD_LOGIC
tob_pkt_active	STD_LOGIC
timeout_1	STD_LOGIC
timeout_n	STD_LOGIC
stop_timeout	STD_LOGIC
timeout_counter	STD_LOGIC_VECTOR ( 15 downto 0 )
timeout_run	STD_LOGIC
pet_timer	STD_LOGIC
clr_build_flag	STD_LOGIC
set_build_flag	STD_LOGIC
clr_chan_len_cnt	STD_LOGIC
inc_corr_counter	STD_LOGIC
build_flag	STD_LOGIC
last_chan_read	STD_LOGIC
any_chan_read	STD_LOGIC
chan_enable_del	STD_LOGIC
finished_lc	STD_LOGIC
reference_lid_0	STD_LOGIC
set_bad_l1id_flag	STD_LOGIC
bad_l1id_flag	STD_LOGIC
l1id_resync_flag	STD_LOGIC
shelf	STD_LOGIC_VECTOR ( 3 downto 0 )
wdog_pet	STD_LOGIC
wdog_overflow_i	STD_LOGIC
tempsig	std_logic
efex_shelf_num	STD_LOGIC_VECTOR ( 1 downto 0 )
set_empty_packet_build	std_logic
empty_pkt_active	std_logic := ' 0 '
ttc_rollover_sig	std_logic := ' 0 '
ttc_rollover_reg	std_logic := ' 0 '
rx_timer_clear	std_logic := ' 0 '
l1id_measure_lock	std_logic := ' 0 '
header_fifo_valid_del	std_logic := ' 0 '
l1id_measure_reg	STD_LOGIC_VECTOR ( 31 downto 0 ) := x " 0000_0000 "
l1id_measure_time	STD_LOGIC_VECTOR ( 31 downto 0 ) := x " 0000_0000 "
l1id_measure_last	STD_LOGIC_VECTOR ( 31 downto 0 ) := x " 0000_0000 "
l1id_measure_max	STD_LOGIC_VECTOR ( 31 downto 0 ) := x " 0000_0000 "
l1id_max_l1id	STD_LOGIC_VECTOR ( 31 downto 0 ) := x " 0000_0000 "
l1id_measure_last_i	STD_LOGIC_VECTOR ( 31 downto 0 ) := x " 0000_0000 "
l1id_measure_max_i	STD_LOGIC_VECTOR ( 31 downto 0 ) := x " 0000_0000 "
timeout_1_raw	std_logic := ' 0 '
timeout_n_raw	std_logic := ' 0 '
timeout_counter_max_i	STD_LOGIC_VECTOR ( 15 downto 0 ) := x " 0000 "
max_chan_i	STD_LOGIC_VECTOR ( 4 downto 0 )
hdr_crc_flag	std_logic := ' 0 '

Instantiations
state_reg	vDFF <Entity vDFF>
event_fifo	event_builder_fifo
timeout	tob_timeout <Entity tob_timeout>
channel_header_crc	hdr_in_crc9 <Entity hdr_in_crc9>
event_header_crc	event_hdr_crc9 <Entity event_hdr_crc9>
event_trailer_crc	event_trailer_CRC20 <Entity event_trailer_CRC20>
chan_trailer_crc	event_trailer_CRC20 <Entity event_trailer_CRC20>
evnt_trailer_err_map	trailer_map <Entity trailer_map>
debug_fifo	event_builder_fifo
dbg_crc9_gen	CRC <Entity CRC>
dbg_crc20_gen	CRC <Entity CRC>
dbg_trailer_err_map	trailer_map <Entity trailer_map>
state_machine_ila	ila_ev_builder
wdog_timer	watchdog <Entity watchdog>

Detailed Description

Definition at line 208 of file ev_builder.vhd.

Member Function Documentation

◆ PROCESS_116()

PROCESS_116	(	clock ,
		reset ,
		current_state ,
		flx_backpressure ,
		flx_bp_enable ,
		header_fifo_valid ,
		chan_enable ,
		current_chan ,
		num_chan ,
		any_chan_read ,
		timeout_1 ,
		timeout_n ,
		s_tvalid ,
		tob_pkt_active ,
		lead_follow_b_reg ,
		chan_in ,
		s_header_mark ,
		s_hdr_crc_tag ,
		comb_error ,
		L1ID_reg_eq ,
		TTC_ignore ,
		L1ID_eq ,
		empty_pkt_active ,
		s_trailer_mark ,
		next_chan ,
		chan_enable_del ,
		chan_crc20_err ,
		chan_len_error ,
		last_chan_read ,
		bad_l1id_flag ,
		first_chan
	)

Process

*** TOB Processor *** Main state machine

note: state numbers are random and do not imply execution order

Definition at line 815 of file ev_builder.vhd.

◆ PROCESS_126()

PROCESS_126	(		clock
	)

Process

corrective trailer - inserted on crc20 or other error occuring mid-channel-packet it makes use of the same channel data crc20 block as normal, but does add in the corr trailer word it uses it's own channel length counter packet spec 0.77 specifies that bit 5 of the MSW is set for corrective trailer, It uses the 6-bit error map because it is replacing the normal FEX trailer which uses the 6-bit map

Definition at line 2055 of file ev_builder.vhd.

◆ PROCESS_135()

PROCESS_135	(		clock
	)

Process

"tob_pkt_active" flag to indicate that an outgoing tob packet has been started, but not finished.
>This is needed in the case that the last channel to be serviced has its data placed in the debug fifo.
>In this case, the state machine must finish the debug packet, and then go back and finish the TOB packet with a trailer and tlast into the tob fifo.

Definition at line 2261 of file ev_builder.vhd.

◆ PROCESS_136()

PROCESS_136	(		clock
	)

Process

"empty_pkt_active" flag to indicate that an empty packet is being built.
an empty packet is built for an event when no tobs have appeared on any channel

Definition at line 2279 of file ev_builder.vhd.

◆ PROCESS_146()

PROCESS_146	(	event_sel( 0 ) ,
		rod_slot
	)

Process

PING PONG EVENT SELECTOR

event_sel(1)	event_sel(0)	slot	Action	Usage
0	0	0	Accept event when ROD slot=L1ID(0)	default ping pong
0	1	0	Accept event when ROD slot= not L1ID(0)	opposite ping pong
0	0	1	Accept event when ROD slot=L1ID(0)	default ping pong
0	1	1	Accept event when ROD slot= not L1ID(0)	opposite ping pong
1	0	X	Accept no events	debug
1	1	X	Accept all events	Only One ROD in use

Definition at line 2881 of file ev_builder.vhd.

◆ PROCESS_147()

PROCESS_147	(		clock
	)

Process

rod_slot = '1' for slot-1 rod_slot = '0' for slot-2

Definition at line 2902 of file ev_builder.vhd.

◆ PROCESS_148()

PROCESS_148	(		clock
	)

Process

L1ID resynchronisation flag this flag is toggled on the last channel of an event where no channel had a matching l1id.
If the flag is set when the next event has a complete l1id mismatch, then a resync is attempted by going back to the first channel and waiting for the timeout_1 period for the arrival of another packet. This is specifically implemented to try to fix the jfex case where the ROD gets ahead by one l1id.

Definition at line 2925 of file ev_builder.vhd.

The documentation for this class was generated from the following file:

ROD/packet_processor/hdl/ev_builder.vhd

Components
event_builder_fifo
event_fifo_ila
ILA_ev_builder
rx_time_ila
header_fifo
hdr_in_crc9	<Entity hdr_in_crc9>
event_hdr_crc9	<Entity event_hdr_crc9>
event_trailer_CRC20	<Entity event_trailer_CRC20>
CRC	<Entity CRC>
trailer_map	<Entity trailer_map>
tob_timeout	<Entity tob_timeout>
watchdog	<Entity watchdog>

Processes

Components

Signals

Instantiations

Detailed Description

Member Function Documentation

◆ PROCESS_116()

note: state numbers are random and do not imply execution order

◆ PROCESS_126()

◆ PROCESS_135()

◆ PROCESS_136()

◆ PROCESS_146()

◆ PROCESS_147()

◆ PROCESS_148()